MN85571AC Datasheet, PDF (14/16 Pages) Panasonic Semiconductor – Single-Chip Audio/Video MPEG2 Encoder

MN85571AC
s Interfaces (continued)
4. Video data input interface
• Interface pin descriptions
Pin Name I/O
Description
VIN[7:0]
I Video data input
Video data must be input in synchronization with the
video data input clock (VCLK).
The format of the input video data must be ITU-R
VCLK
BT.656 (level D1, 4:2:2).
I Video data input clock input
The video data input to this product assumes that the input signal has been time base corrected (TBC) in the stage
prior to this product.
This product also assumes that the PCM data input and the video data input are locked in the stage prior to this product.
5. PCM data input (audio data input) interface
The PCM data input interface is provided for input of the audio data (PCM coded data) to the audio encoding block.
This product performs encoding for audio data that is sampled at a sampling frequency of 48 kHz.
It uses either Dolby Digital or linear PCM as the encoding technique.
There are limitations on the PCM data input quantization word length depending on the encoding technique used.
For Dolby Digital processing, this product supports 16, 18, 20, and 24-bit quantizations. For linear PCM process-
ing it only supports 16-bit quantization.
This product supports 2-channel (left/right) audio, and data is 1-bit serial data transmitted MSB first.
This product supports the I2S, left justified, and right justified formats as input formats.
The PCM data input interface can be switched between two modes: master mode and slave mode.
In master mode, a PCM master clock signal (256 or 384 fs) is input to this product’s PCKI pin and used to create the
output PCM master clock output signal, the bit clock signal, and the left/right channel discrimination clock signal for
the external A/D converter. These signals are output from the PCKO, BCKIO, and LRCKIO pins, respectively.
In slave mode, the PCKI, BCKIO, and LRCKIO pins are used to input a PCM master clock signal (256 or 384 fs),
bit clock signal, and a left/right channel discrimination clock signal, respectively. (In this mode, the PCKO pin must
be left open (N.C.).)
All the PCM data input interface parameter settings are set from multiplexing block SRISC microcode.
• Interface pin descriptions
Pin Name
BCKIO
LRCKIO
ADIN
PCKI
PCKO
I/O
Description
I/O Bit clock output
I/O Left/right channel discrimination clock output
I PCM data (audio data) input
I PCM master clock input
O PCM master clock output
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SDD00023AEM