MN85571AC Datasheet, PDF (10/16 Pages) Panasonic Semiconductor – Single-Chip Audio/Video MPEG2 Encoder

MN85571AC
s Interfaces
1. Host interface
Accesses to this product’s internal resources from an external host take place using the host interface block (HIF).
There are two techniques for accessing resources over the host interface as follows.
1) Direct addressing access
2) Indirect addressing access
1) Direct addressing access
[Read]
• Timing chart
t_rcyc
HA[3:0]
NHCS
NHRE
HD[15:0]
t_csda
t_csgat
Valid Data
t_csad
t_adcs
t_reda
t_csdhd
t_read
"Hi-Z"
t_adre
t_regat
t_dhd
Valid Data
"Hi-Z"
"H"
NHWE
• AC Characteristics
Item
Read cycle time
HA[3:0] setup time from the NHCS falling edge
HA[3:0] setup time from the NHRE falling edge
HD[15:0] bus drive start time from the NHCS falling edge
HD[15:0] bus drive start time from the NHRE falling edge
HD[15:0] valid data output time from the NHCS falling edge
HD[15:0] valid data output time from the NHRE falling edge
HA[3:0] hold time from the NHCS rising edge
HA[3:0] hold time from the NHRE rising edge
HD[15:0] valid data hold time from the NHCS rising edge
HD[15:0] valid data hold time from the NHRE rising edge
Symbol Min Typ Max Unit
t_rcyc
200 

ns
t_adcs
0

ns
t_adre
0

ns
t_csgat


2
ns
t_regat


2
ns
t_csda

 135
ns
t_reda

 135
ns
t_csad
40


ns
t_read
40


ns
t_csdhd
2

ns
t_dhd
2

ns
10
SDD00023AEM