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| MN103LF66 Datasheet, PDF (82/102 Pages) Panasonic Semiconductor – 32-bit Single-chip Microcontroller | |||
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MN103LF66/67/68/69/70/71/72/73/74/75/76/77/78/79 Series
32-bit Single-chip Microcontroller
PubNo. 2347901-012E
Parameter
Symbol
Conditions
Address/Data Separate mode. Refer to Figure:1.6.7, Figure:1.6.8. *16
F18
Read enable signal
pulse width (NRE)
tREW
At fixed wait
tHREW At handshake
F19
Write enable signal falling
delay time (NWE[1:0])
tWEDF
F20
Write enable signal
pulse width (NWE[1:0])
tWEW
At fixed wait
tHWEW At handshake
VDD50 = AVDD = VREFH = 2.2 V to 5.5 V
VSS = 0 V, CL = 50 pF
Ta = -40 ï°C to +105 ï°C
Rating
MIN
TYP
Unit
MAX
t CYC
nfr
x (REN-EA)-10
t CYC
nfr
x (REN+1)-10
t CYC
nfr
x (BCS+EA)-10
ns
t CYC
nfr
x (WEN-EA)-10
t CYC
nfr
x (WEN+1)-10
*16 The values of F7 to F20 are guaranteed on the condition of VDD50 = 3.3 V and VSS = 0 V.
SYSCLK
NRE
t REDF
t REW
t HREW
A[20:0]
t AD
t AH
NCS[2:1]
D[15:0]
t CSDF
t RDS
t CSDR
t RDH
NDK
t DKS
t DKH
Figure:1.6.7 Separate Address/Data Synchronous Mode Read Timing
Publication date: November 2015
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