MN103LF66 Datasheet, PDF (81/102 Pages) Panasonic Semiconductor – 32-bit Single-chip Microcontroller

MN103LF66/67/68/69/70/71/72/73/74/75/76/77/78/79 Series
32-bit Single-chip Microcontroller
PubNo. 2347901-012E
Parameter
Symbol
Conditions
Address/Data Separate mode. Refer to Figure:1.6.7, Figure:1.6.8. *16
F7
Address delay time
(A[20:0])
t_AD
V_DD50 = AV_DD = V_REFH = 2.2 V to 5.5 V
V_SS = 0 V, C_L = 50 pF
Ta = -40 C to +105 C
Rating
MIN
TYP
Unit
MAX
t CYC
nfr
x EA-10
F8
Address hold time
(A[20:0])
At reading
t CYC
nfr
x (BCE-REN)-10
t_AH
At writing
t CYC
nfr
x (BCE-WEN)-10
F9
Chip select signal falling
delay time (NCS[2:1])
t_CSDF
t CYC
nfr
x EA-10
F10
Chip select signal rising
delay time (NCS[2:1])
t_CSDR
At reading
At writing
t CYC
nfr
x (BCE-REN)-10
t CYC
nfr
x (BCE-WEN)-10
F11
Read data setup time
(D[15:0])
t_RDS
60
ns
F12
Read data hold time
(D[15:0])
t_RDH
0
F13
Write data setup time
(D[15:0])
t_WDS
t CYC
nfr
x (WEN-EA)-15
F14
Write data hold time
(D[15:0])
t_WDH
F15
Data acknowledge signal
setup time (NDK)
F16
Data acknowledge signal
hold time (NDK)
F17
Read enable signal falling delay time
(NRE)
t_DKS
t_DKH
t_REDF
t CYC
nfr
x (BCE-WEN)-15
50
0
t CYC
nfr
x (BCS+EA)-10
Publication date: November 2015