MN103LF66 Datasheet, PDF (4/102 Pages) Panasonic Semiconductor – 32-bit Single-chip Microcontroller

MN103LF66/67/68/69/70/71/72/73/74/75/76/77/78/79 Series
32-bit Single-chip Microcontroller
PubNo. 2347901-012E
1.3 Hardware Functions
CPU core
MN103L core (The instruction set is compatible MN103S series)
Memory space 4 GB (instruct/data common use)
LOAD-STORE architecture (3-stage pipeline)
Machine cycle
High-speed mode 20.8 ns/ 48 MHz (Max)
Low-speed mode 30.5 s/ 32.768 kHz (Max)
Operation mode
NORMAL mode (CPU clock operation, Peripheral circuit clock operation mode)
SLOW mode (CPU clock operation, Peripheral circuit clock operation mode)
HALT mode
(CPU clock stop, Peripheral circuit clock operation mode)
STOP mode
(All clocks stop mode)
Clock oscillation circuit : 5 circuits
External high-speed oscillation (clkosc) : Crystal oscillator/ Ceramic oscillator
: 4 MHz to 20 MHz
External low-speed oscillation (clkx) : Crystal oscillator/ Ceramic oscillator
: 32.768 kHz
Internal high-speed oscillation (clkrc) : 20 MHz
Internal low-speed oscillation (clkrcx) : 30 kHz
PLL output (clkpll)
: 60 MHz to 120 MHz
Clock multiple circuit (PLL)
Multiplication rate:
4, 6, 8, 10, 12, 16, 20 multiplied clock of clkoscsel
2440 to 3660 multiplied clock of clkx
Clock dividing
2, 3 divided of clkpll
PLL output dividing clock: 20 MHz to 48 MHz (clkplldiv)
Publication date: November 2015