OX12PCI840 Datasheet, PDF (9/33 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX12PCI840
4 PCI TARGET CONTROLLER
4.1 Operation
The OX12PCI840 responds to the following PCI
transactions:-
• Configuration access: The OX12PCI840 responds to
type 0 configuration reads and writes if the IDSEL
signal is asserted and the bus address is selecting the
configuration registers for function 0. The device will
respond to the configuration transaction by asserting
DEVSEL#. Data transfer then follows. Any other
configuration transaction will be ignored by the
OX12PCI840.
• IO reads/writes: The address is compared with the
addresses reserved in the I/O Base Address Registers
(BARs). If the address falls within one of the assigned
ranges, the device will respond to the IO transaction
by asserting DEVSEL#. Data transfer follows this
address phase. Only byte accesses are possible to
the function BARs (excluding the local configuration
registers for which WORD, DWORD access is
supported). For IO accesses to these regions, the
controller compares AD[1:0] with the byte-enable
signals as defined in the PCI specification. The access
is always completed; however if the correct BE signal
is not present the transaction will have no effect.
• Memory reads/writes: These are treated in the same
way as I/O transactions, except that the memory
ranges are used. Memory access to single-byte
regions is always expanded to DWORDs in the
OX12PCI840. In other words, OX12PCI840 reserves
a DWORD per byte in single-byte regions. The device
allows the user to define the active byte lane using
LCC[4:3] so that in Big-Endian systems the hardware
can swap the byte lane automatically. For Memory
mapped access in single-byte regions, the
OX12PCI840 compares the asserted byte-enable with
the selected byte-lane in LCC[4:3] and completes the
operation if a match occurs, otherwise the access will
complete normally on the PCI bus, but it will have no
effect on either the parallel port or the local bus
controller.
• All other cycles (64-bit, special cycles, reserved
encoding etc.) are ignored.
The OX12PCI840 will complete all transactions as
disconnect-with-data, i.e. the device will assert the STOP#
signal alongside TRDY#, to ensure that the Bus Master
does not continue with a burst access. The exception to
this is Retry, which will be signalled in response to any
access while the OX12PCI840 is reading from the serial
EEPROM.
The OX12PCI840 performs medium-speed address
decoding as defined by the PCI specification. It asserts the
DEVSEL# bus signal two clocks after FRAME# is first
sampled low on all bus transaction frames which address
the chip. Fast back-to-back transactions are supported by
the OX12PCI840 as a target, so a bus master can perform
faster sequences of write transactions to the parallel port
when an inter-frame turn-around cycle is not required.
The device supports any combination of byte-enables to
the PCI Configuration Registers and the Local
Configuration registers (see Base Address 2 and 3). If a
byte-enable is not asserted, that byte is unaffected by a
write operation and undefined data is returned upon a read.
The OX12PCI840 performs parity generation and checking
on all PCI bus transactions as defined by the standard. If a
parity error occurs during the PCI bus address phase, the
device will report the error in the standard way by asserting
the SERR# bus signal. However if that address/command
combination is decoded as a valid access, it will still
complete the transaction as though the parity check was
correct.
The OX12PCI840 does not support any kind of caching or
data buffering, other than that in the parallel port interface
itself.
4.2 Configuration space
The OX12PCI840 is a single function device, with one
configuration space. All required fields in the standard
header are implemented, plus the Power Management
Extended Capability register set. The format of the
configuration space is shown in Table 2 overleaf.
In general, writes to any registers that are not implemented
are ignored, and all reads from unimplemented registers
return 0.
DS-0021 Jun 05
Page 9