OX12PCI840 Datasheet, PDF (15/33 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX12PCI840
4.4.5 Global Interrupt Status and Control Register ‘GIS’ (Offset 0x10)
Bits Description
Read/Write
EEPROM _PCI
1:0 Reserved
-
R
2
MIO0 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
-
R
reflects the non-inverted or inverted state of MIO0 pin.
3
MIO1 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
-
R
reflects the non-inverted or inverted state of MIO0 pin.
17-4 Reserved
-
R
18 MIO0 INTA enable
W
RW
When set (1) allows MIO0 to assert a PCI interrupt on the INTA line. State of
MIO0 that causes an interrupt is dependant upon the polarity set by MIC(1:0)
19 MIO1 INTA enable
W
RW
When set (1) allows MIO1 to assert a PCI interrupt on the INTA line. State of
MIO1 that causes an interrupt is dependant upon the polarity set by MIC(3:2)
20 Power-down Interrupt This is a sticky bit. When set, it indicates a power-down
-
R
request issued and would normally have asserted a PCI interrupt if bit 21 was
set (see section 7.9). Reading this bit clears it.
21 Power-down interrupt enable. When ‘1’ a power down request is allowed to W
RW
generate an interrupt.
22 Parallel port interrupt status
-
R
23 Parallel port interrupt enable
W
RW
31:24 Reserved
-
R
Reset
0x0h
X
X
0
0
0
X
0
0
1
000h
DS-0021 Jun 05
Page 15