OX12PCI840 Datasheet, PDF (7/33 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX12PCI840
Pin Numbers
Dir¹ Name
Description
Multi-purpose & External interrupt pins
82, 51
I/O
EEPROM pins
81
O
78
O
80
IU
79
O
Miscellaneous pins
77
I
Power and ground²
8,30,40,56,97
V
16,45,67,87
V
3,7,20,29,35,41,48,55,61,72,92,96 G
15,44,66,85
G
MIO[1:0]
Multi-purpose I/O pins. Can drive high or low, or assert a PCI
interrupt
EE_CK
EE_CS
EE_DI
EE_DO
EEPROM clock
EEPROM active-high Chip Select
EEPROM data in. When the serial EEPROM is connected,
this pin should be pulled up using 1-10k resistor. When the
EEPROM is not used the internal pull-up is sufficient.
EEPROM data out.
TEST
Test Pin : should be held low at all times
AC VDD
DC VDD
AC GND
DC GND
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Supplies GND to output buffers in switching (AC) state
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
Table 1: Pin Descriptions
Note 1: Direction key:
I
Input
ID
Input with internal pull-down
O
Output
I/O Bi-directional
OD Open drain
NC No connect
Z
High impedance
P_I
P_O
P_I/O
P_OD
PCI input
PCI output
PCI bi-directional
PCI open drain
G
Ground
V
5.0V power
Note 2: Power & Ground
There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI and Local Bus
pins.
DS-0021 Jun 05
Page 7