OX12PCI840 Datasheet, PDF (18/33 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX12PCI840
5 BI-DIRECTIONAL PARALLEL PORT
5.1 Operation and Mode selection
The OX12PCI840 offers a compact, low power, IEEE-1284
compliant host-interface parallel port, designed to interface
to many peripherals such as printers, scanners and
external drives. It supports compatibility modes, SPP,
NIBBLE, PS2, EPP and ECP modes. The register set is
compatible with the Microsoft® register definition. The
system can access the parallel port via two blocks of I/O
space; BAR0 (8 bytes) contains the address of the basic
parallel port registers, BAR1 (4 bytes) contains the address
of the upper registers. These are referred to as the ‘lower
block’ and ‘upper block’ in this section. If the upper block is
located at an address 0x400 above the lower block,
generic PC device drivers can be used to configure the
port, as the addressable registers of legacy parallel ports
always have this relationship. If not, a custom driver will be
needed.
5.1.1 SPP mode
SPP (output-only) is the standard implementation of a
simple parallel port. In this mode, the PD lines always drive
the value in the PDR register. All transfers are done under
software control. Input must be performed in nibble mode.
Generic device driver-software may use the address in I/O
space encoded in BAR0 of function 1 to access the parallel
port. The default configuration allocates 8 bytes to BAR0 in
I/O space.
5.1.2 PS2 mode
This mode is also referred to as bi-directional or compatible
parallel port. In this mode, directional control of the PD
lines is possible by setting & clearing DCR[5]. Otherwise
operation is similar to SPP mode.
5.1.3 EPP mode
To use the Enhanced Parallel Port ‘EPP’ the mode bits
(ECR[7:5]) must be set to ‘100’. The EPP address and data
port registers are compatible with the IEEE 1284 definition.
A write or read to one of the EPP port registers is passed
through the parallel port to access the external peripheral.
In EPP mode, the STB#, INIT#, AFD# AND SLIN# pins
change from open-drain outputs to active push-pull (totem
pole) drivers (as required by IEEE 1284) and the pins
ACK#, AFD#, BUSY, SLIN# and STB# are redefined as
INTR#, DATASTB#, WAIT#, ADDRSTB# and WRITE#
respectively.
An EPP port access begins with the host reading or writing
to one of the EPP port registers. The device automatically
buffers the data between the I/O registers and the parallel
port depending on whether it is a read or a write cycle.
When the peripheral is ready to complete the transfer it
takes the WAIT# status line high. This allows the host to
complete the EPP cycle.
If a faulty or disconnected peripheral failed to respond to an
EPP cycle the host would never see a rising edge on
WAIT#, and subsequently lock up. A built-in time-out facility
is provided in order to prevent this from happening. It uses
an internal timer which aborts the EPP cycle and sets a
flag in the PSR register to indicate the condition. When the
parallel port is not in EPP mode the timer is switched off to
reduce current consumption. The host time-out period is
10μs as specified with the IEEE-1284 specification.
The register set is compatible with the Microsoft® register
definition. Assuming that the upper block is located 400h
above the lower block, the registers are found at offset
000-007h and 400-402h.
5.1.4 ECP mode
The Extended Capabilities Port ‘ECP’ mode is entered
when ECR[7:5] is set to ‘011’. ECP mode is compatible
with Microsoft® register definition of ECP, and IEEE-1284
bus protocol and timing. This implementation of the ECP
port supports the optional decompression of received
compressed data, but does not compress transmit data.
Assuming that the upper block is located 400h above the
lower block, the registers are found at offset 000-007h and
400-402h.
5.2 Parallel port interrupt
The parallel port interrupt is asserted on INTA#. It is
enabled by setting DCR[4]. When DCR[4] is set, an
interrupt is asserted on the rising edge of the ACK#
(INTR#) pin and held until the status register is read, which
resets the INT# status bit (DSR[2]).
DS-0021 Jun 05
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