OX12PCI840 Datasheet, PDF (19/33 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX12PCI840
5.3 Register Description
The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block).
Register
Name
PDR
ecpAFifo
DSR
(EPP mode)
Address R/W Bit 7 Bit 6 Bit 5 Bit 4
Bit 3 Bit 2
Offset
SPP (Compatibility Mode) Registers
000h R/W
Parallel Port Data Register
000h R/W
ECP FIFO : Address / RLE
001h
R nBUSY ACK#
PE
SLCT ERR# INT#
(Other modes) _001h
R nBUSY ACK#
PE
SLCT ERR# INT#
DCR
002h R/W
0
0
DIR INT_EN nSLIN# INIT#
EPPA ¹
003h R/W
EPP Address Register
EPPD1 ¹
004h R/W
EPP Data 1 Register
EPPD2 ¹
005h R/W
EPP Data 2 Register
EPPD3 ¹
006h R/W
EPP Data 3 Register
EPPD4 ¹
007h R/W
EPP Data 4 Register
EcpDFifo 400h R/W
ECP Data FIFO
TFifo
400h R/W
Test FIFO
CnfgA
400h
R
Configuration A Register – always 90h
CnfgB
401h
R
0
int
‘000000’
ECR
402h R/W
Mode[2:0]
Must write ‘00001’
-
403h
-
Reserved
Table 6: Parallel port register set
Note 1 : These registers are only available in EPP mode.
Note 2 : Prefix ‘n’ denotes that a signal is inverted at the connector. Suffix ‘#’ denotes active-low signalling
Bit 1 Bit 0
1 Timeout
1
1
nAFD# nSTB#
The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX). The reset value of DSR is ‘XXXXX111’. DCR and
ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
5.3.1 Parallel port data register ‘PDR’
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 will drive data onto the parallel port data lines.
In all other modes the drivers may be tri-stated by setting
the direction bit in the DCR. Reads from this register return
the value on the data lines.
5.3.2 ECP FIFO Address / RLE
A data byte written to this address will be interpreted as an
address if bit(7) is set, otherwise an RLE count for the next
data byte. Count = bit(6:0) + 1.
5.3.3 Device status register ‘DSR’
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
from the peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 5.1.3)
DSR[0]:
EPP mode: Timeout
logic 0 ⇒Timeout has not occurred.
logic 1 ⇒Timeout has occurred (Reading this bit clears it).
Other modes: Unused
This bit is permanently set to 1.
DSR[1]: Unused
This bit is permanently set to 1.
DS-0021 Jun 05
Page 19