OX12PCI840 Datasheet, PDF (13/33 Pages) List of Unclassifed Manufacturers – Integrated Parallel Port and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX12PCI840
4.4.2 Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
This register configures the operation of the multi-purpose I/O pins ‘MIO[1:0] as follows.
Bits
Description
1:0
MIO0 Configuration Register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
Read/Write
EEPROM
PCI
W
RW
3:2
MIO1 Configuration Register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
W
RW
4
MIO0_PME Enable. A value of ‘1’ enables MIO0 pin to set the
W
RW
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO0 from setting the PME_Status bit.
5
MIO1_PME Enable. A value of ‘1’ enables MIO1 pin to set the
W
RW
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO1 from setting the PME_Status bit.
6
MIO0 Power Down Request: A ‘1’ enables MIO0 to control the power
W
RW
down request filter.
7
MIO1 Power Down Request: A ‘1’ enables MIO1 to control the power
W
RW
down request filter.
31:8
Reserved
-
R
Reset
00
00
0
0
0
0
00
4.4.3 Local Bus Timing Parameter register 1 ‘LT1’ (Offset 0x08):
The Local Bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the internal local
bus (that connects to the parallel port). It is envisaged that these should not need to be changed by the user. The timing
parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local Bus control signals. The values
programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events occur, where
the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The timings refer to I/O or Memory
mapped accesses.
Bits
3:0
7:4
11:8
15:12
19:16
23:20
27:24
31:28
Description
Read Cycle start
Read Cycle end
Write Cycle start
Write Cycle end
Read Assertion
Read De-assertion
Write Assertion
Write De-assertion
Read/Write
EEPROM _PCI
W
RW
W
RW
W
RW
W
RW
W
RW
W
RW
W
RW
W
RW
Reset
0h
2h
0h
2h
1h
2h
1h
2h
Note 1: Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. See notes in the following page.
DS-0021 Jun 05
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