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TCC-206 Datasheet, PDF (9/33 Pages) ON Semiconductor – Six-Output PTIC Control IC | |||
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TCCâ206
Boost Control
The TCCâ206 integrates an asynchronous current control
boost converter. It operates in a discontinuous mode and
features spreadâspectrum circuitry for ElectroâMagnetic
Interference (EMI) reduction. The average boost clock is
2 MHz and the clock is spread between 0.8 MHz and 4 MHz.
Boost Output Voltage (VHV) Control Principle
The asynchronous control starts the boost converter as
soon as the VHV voltage drops below the reference set by
the 4âbit DAC and stops the boost converter when the VHV
voltage rises above the reference again.
Due to the slow response time of the control loop, the
VHV voltage may drop below the set voltage before the
control loop compensates for it. In the same manner, VHV
can rise higher than the set value. This effect may reduce the
maximum output voltage available. Please refer to Figure 7
below.
The asynchronous control reduces switching losses and
improves the output (VHV) regulation of the DC/DC
converter under light load, particularly in the situation
where the TCCâ206 only maintains the output voltages to
fixed values.
CHV
Recharge
CHV
Discharge
VHV
Set
VHV
Delay
Delay
Boost
Running
Figure 6. VHV Voltage Waveform
Delay
Time
High Impedance (High Z) Feature
In shutdown mode the OUT pins are set to a high
impedance mode (high Z). Following is the principle of
operation for the control IC:
1. The DAC output voltage VOUT is defined by:
DAC code
VOUT + 255
24 V 2
(eq. 1)
2. The voltage VHV defines the maximum supply
voltage of the DAC supply output regulator and is
set by a 4âbit control.
3. The maximum DAC DC output voltage VOUT is
limited to (VHV â 2 V).
4. The minimum output DAC voltage VOUT is 1.0 V
max.
Figure 7. DAC Output Range Example A
Figure 8. DAC Output Range Example B
Digital Interface
The control IC is fully controlled through a digital
interface (DATA, CLK, CS). The digital interface autoâ
matically detects and responds to MIPI RFFE interface
commands, 3âwire 30âbit serial interface commands or
3âwire 32âbit serial interface commands. Autoâdetection is
accomplished on a frame by frame basis. The digital
interface is described in the following sections of this
document, for detailed programming instructions please
refer to the programming guide, available by contacting
ON Semiconductor.
3âWire Serial Interface
The 3âwire serial interface operates in a synchronous
writeâonly 3âwire slave mode. 30âbit or 32âbit message
length is automatically detected for each frame. If CS
changes state before all bits are received then all data bits are
ignored. Data is transmitted most significant bit first and
DATA is latched on the rising edge of CLK. Commands are
latched on the falling edge of CS.
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