TCC-206 Datasheet, PDF (26/33 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−206
In Figure 18, TRIG edge 2, will transfer “MESSAGE A2”, “MESSAGE B1”, and “MESSAGE C1” to the respective outputs,
but will ignore “MESSAGE A1”.
Figure 18. Sequences of Triggers and Messages to Different Outputs
Table 30. TRIG_LAT PARAMETER TIMING
Symbol
Description
Min
TRIG_LAT Latency following the falling edge of last clock cycle of a certain message, until
5
the moment a TRIG edge is allowed to update the value sent by that message
Max
Unit
25
ns
Register RFFE:
RFFE_REG_0x11
Address RFFE A[4:0]:
0x11
Bits
Reset
7
6
5
4
3
2
1
0
Reserved
TRIG SEL
Reserved
TRIG Edge _{MASK EXT TRIG}
(1) (2)
U-0
U-0
U-0
W-1
U−0
U−0
W−1
W−1
(1) Following sequence is required when changing the expected polarity of TRIG pin:
a) TRIG_SEL = ‘1’ (disable TRIG pin)
b) TRIG_EDGE = new value
c) TRIG_SEL = ‘0’ (enable TRIG pin)
(2) After power−up, first configure TRIG_Edge, then write TRIG_SEL = ‘0’ Bit 4: TRIG Select
0: Use external TRIG pin. Sending the RFFE message will load a ’shadow’ registers only. Only upon an
active signal on external TRIG pin are the output registers loaded with the new voltage settings which
are then applied to the outputs. Software triggers generated by bits [2:0] of RFFE_REG_0x1C are
ignored when external TRIG pin is selected.
1: External TRIG pin will not be used. (default)
Bit [1]: TRIG edge
0: TRIG pin active falling
1: TRIG pin active rising (default)
Bit [0]: MASK EXT TRIG
0: External trigger is not masked
1: Mask external trigger pin (default)
Turbo mode timing is controlled by these registers:
Register RFFE:
RFFE_REG_0x12
Address RFFE A[4:0]:
0x12
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
2
1
0
Bits
Reserved
TC_STP_DAC_C
TC_STP_DAC_B
TC_STP_DAC_A
Reset
U−0
U−0
W−0
W−1
W−0
W−1
W−0
W−1
Register RFFE:
RFFE_REG_0x13
Address RFFE A[4:0]:
0x13
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
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