TCC-206 Datasheet, PDF (25/33 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−206
Register RFFE:
RFFE_REG_0x10
Address RFFE A[4:0]:
0x10
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
2
1
0
Bits
Reset
Reserved
U−0
U−0
U−0
Fixed
U−1
W−1
Boost voltage value
W−0
W−1
W−1
Bit [3:0]: Boost voltage value
Refer to Table 19 for values
The MIPI RFFE Trigger Modes can be used as a synchronization signal to ensure that new DAC settings are applied to the
outputs at appropriate times in the overall transceiver system. When the RFFE TRIG function is enabled via the TRIG SEL
bit of RFFE_REG_0x11the requested DAC voltage levels are set up in the shadow registers and not transferred to the
destination registers until the trigger condition is met. In this manner the change in output voltage levels are synchronized with
the RFFE TRIG command. The trigger configuration also provides for an external TRIG pin to be used as a synchronization
signal. When the TRIG input pin is enabled via the TRIG SEL bit of RFFE_REG_0x11the requested DAC voltage levels are
set up in the shadow registers and are not transferred to the destination registers until the external trigger condition is met. In
this manner the change in output voltage levels are synchronized with the external TRIG event. The external TRIG input is
referenced to VIO. To improve interfacing options the polarity of external TRIG is programmable via TRIG_edge bit of
RFFE_REG_0x11. When MIPI RFFE trigger and the external TRIG input are disabled by
MASK_EXT_TRIG of RFFE_REG_0x11 and TRIGGER_MASK[5:3] of RFFE_REG_0x1C, the requested DAC voltage
levels are immediately applied to the outputs and are not synchronized with the RFFE Trigger Modes or the external TRIG
signal.
When valid trigger edge occurs, only the completely received messages are subject to be applied to the outputs.
A message is considered to be completed, if the TRIG edge occurs after TRIG_LAT following last SDL clock falling edge
in the frame.
In Figure 17, the last SDL clock cycle in each frame is highlighted gray.
The parameter TRIG_LAT is represented as the latency following the SDL last falling edge in the frame until TRIG edge
occurs.
As an example, in Figure 17 TRIG edge 3 occurs before TRIG_LAT, following last SDL falling edge in frame of
“MESSAGE A3”, so TRIG edge 3 will move “MESSAGE A2” to output, instead of “MESSAGE A3”. In this case TRIG edge
3 has the same effect as TRIG edge 2, which is described below.
If trigger edge occurs while a message frame is being received by the slave on the serial bus, than the pending message will
not be transferred to the output until next trigger edge occurs after frame transfer is completed.
A pending message is considered from the moment SSC cycle starts, until after TRIG_LAT following last SDL falling edge
in the frame.
For example, in Figure 17, both TRIG edge 2 and TRIG edge 3 occur while “MESSAGE A3” is pending. In this case both
will have same effect, which is to transfer “MESSAGE A2” to the output.
“MESSAGE A3” will be transferred to the output by TRIG edge 4, because it occurs after TRIG_LAT.
If more than one message was received before a trigger edge, than only the last completed message will be transferred to
the output.
For example, in Figure 17, between TRIG edge 1 and TRIG edge 2, there have been two messages sent: “MESSAGE A1”
and “MESSAGE A2”. In this case, “MESSAGE A1” will be ignored, and only “MESSAGE A2” will be transferred to the
output by TRIG edge 2.
Figure 17. Sequences of Triggers and Messages to Same Output
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