N34C04 Datasheet, PDF (9/11 Pages) ON Semiconductor – 4-Kb Serial SPD EEPROM for DDR4 DIMM

N34C04
Table 11a. SWP SET COMMAND DETAIL (following Slave Address)
Command
Block(x)
Protection
Slave
Response
Address
Byte
Slave
Response
SWPx(Note 13)
Not Set
ACK
(Dummy)
ACK
Set
NoACK
(Dummy)
NoACK
CWP
X
ACK
(Dummy)
ACK
Data Byte
(Dummy)
(Dummy)
(Dummy)
Slave
Response
ACK
NoACK
ACK
Write
Cycle
Yes
No
Yes
Table 11b. SWP QUERRY COMMAND DETAIL (following Slave Address)
Command
Block(x)
Protection
Slave
Response
Data Byte
Master
(Response)
RPSx (Nots 13, 14)
Not Set
ACK
Dummy
(NoACK)
Set
NoACK
Dummy
(NoACK)
Data Byte
Dummy
Dummy
Master
(Response)
(NoACK)
(NoACK)
Table 11c. SPD PAGE SELECT COMMAND DETAIL (following Slave Address)
Command
SPD Active
Page
Slave
Response
Address
Byte
Slave
Response
SPAx (Notes 15, 16)
X
ACK
(Dummy)
ACK
Data Byte
(Dummy)
Slave
Response
NoACK
Write
Cycle
No
Table 11d. SPD ACTIVE PAGE QUERRY COMMAND DETAIL (following Slave Address)
Command
SPD Active
Page
Slave
Response
Data Byte
Master
(Response)
Data Byte
Master
(Response)
RPA
0
ACK
Dummy
(NoACK)
Dummy
(NoACK)
(Notes 13, 14, 17)
1
NoACK
Dummy
(NoACK)
Dummy
(NoACK)
13. The Master can terminate the sequence by issuing a STOP once the N34C04 responds with NoACK
14. The Master can terminate the sequence by responding with (NoACK) followed by STOP after any dummy data byte.
15. Setting the SPD Page Address to ‘0’ selects the lower 2−Kb EEPROM bank, setting it to ‘1’ selects the upper 2−Kb EEPROM bank.
16. The lower 2−Kb EEPROM bank (corresponding to SPD page address ‘0’) is active (visible) immediately following power−up.
17. The device will respond with ACK when the lower 2−Kb EEPROM bank is active and with NoACK when the upper 2−Kb EEPROM bank is
active.
BUS ACTIVITY: S
T
A
MASTER ^R
T
SDA LINE
SLAVE
ADDRESS
Dummy
ADDRESS
S
Dummy
T
DATA
O
P
SLAVE
X = Don’t Care
AN
C or O
KA
C
K
AN
C or O
KA
C
K
AN
C or O
KA
C
K
Figure 12. SWP & SPA Timing
BUS ACTIVITY: S
T
A
MASTER ^R
T
SDA LINE
SLAVE
ADDRESS
N
N
O
OS
A
AT
C
CO
K
KP
SLAVE
X = Don’t Care
AN
C or O
KA
C
K
Dummy
DATA
Dummy
DATA
Figure 13. RPS & RPA Timing
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