N34C04 Datasheet, PDF (1/11 Pages) ON Semiconductor – 4-Kb Serial SPD EEPROM for DDR4 DIMM

N34C04
4-Kb Serial SPD EEPROM
for DDR4 DIMM
Description
The N34C04 is a 4−Kb serial EEPROM, which implements the
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD)
specification for DDR4 DIMMs and supports the Standard (100 kHz),
Fast (400 kHz) and Fast Plus (1 MHz) I²C protocols.
One of the two available 2−Kb EEPROM banks (referred to as SPD
pages in the EE1004−v specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb EEPROM blocks can be Write
Protected by software command.
Features
• JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD) Compliant
• Temperature Range: −40°C to +125°C
• Supply Range: 1.7 V − 3.6 V
• I²C / SMBus Interface
• Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Low Power CMOS Technology
• 2 x 3 x 0.5 mm UDFN Package
• These Devices are Pb−Free and are RoHS Compliant
V_CC
SCL
A₂, A₁, A₀
WP
N34C04
SDA
V_SS
Figure 1. Functional Symbol
www.onsemi.com
1
UDFN8
MU3 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A₀
1
A₁
(Top View)
A₂
V_SS
V_CC
WP
SCL
SDA
UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
D2U
AZZ
YM
G
UDFN8
D2U
A
ZZ
Y
M
G
= Specific Device Code
= Assembly Location Code
= Assembly Lot Number (Last Two Digits)
= Production Year (Last Digit)
= Production Month (1 − 9, O, N, D)
= Pb−Free Package
PIN FUNCTIONS
Pin Name
Function
A₀, A₁, A₂
SDA
SCL
WP
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
V_CC
V_SS
DAP
Power Supply
Ground
Backside Exposed DAP at V_SS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
November, 2016 − Rev. 0
Publication Order Number:
N34C04/D