N34C04 Datasheet, PDF (4/11 Pages) ON Semiconductor – 4-Kb Serial SPD EEPROM for DDR4 DIMM

N34C04
Table 8. INPUT IMPEDANCE
Symbol
Parameter
Z_IL
Input Impedance for A0, A1, A2, WP Pins
Z_IH
Input Impedance for A0, A1, A2, WP Pins
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA: The Serial Data I/O pin receives input data and transmits
data stored in the memory. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is delivered
on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor. The Write Protect pin should be tied
directly either to Vcc or GND.
Power−On Reset (POR)
The N34C04 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up to an
undetermined logic state. As V_CC exceeds the POR trigger
level, the device will power up into standby mode. The
device will power down into Reset mode when V_CC drops
below the POR trigger level. This bi−directional POR
behavior protects the N34C04 against brown−out failure
following a temporary loss of power. The POR trigger level
is set below the minimum operating V_CC level.
Device Interface
The N34C04 supports the Inter−Integrated Circuit (I²C)
and the System Management Bus (SMBus) data
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing a
2−wire data bus. Data flow is controlled by a Master device,
which generates the serial clock and the START and STOP
conditions. The N34C04 acts as a Slave device. Master and
Slave alternate as transmitter and receiver. Up to 8 N34C04
devices may be present on the bus simultaneously, and can be
individually addressed by matching the logic state of the
address inputs A0, A1, and A2.
I²C/SMBus Protocol
The I²C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the V_CC
Test Conditions
V_IN < 0.3 * Vcc
V_IN > 0.7 * Vcc
Min
Max
Unit
30
kW
800
kW
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) determine whether the command is a read/write
command (1010b) or a utility command (0110b), as
described in Table 9. The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W, specifies
whether a Read (1) or Write (0) operation is being performed.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9^th clock
cycle (Figure 3). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9^th clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 4.
SDA
SCL
START BIT
Figure 2. Start/Stop Timing
STOP BIT
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