N34C04 Datasheet, PDF (3/11 Pages) ON Semiconductor – 4-Kb Serial SPD EEPROM for DDR4 DIMM

N34C04
Table 5. A.C. CHARACTERISTICS (Note 6) V_CC = 1.7 V to 3.6 V, T_A = −40°C to +125°C, unless otherwise specified.
Standard
V_CC = 1.7 V − 3.6 V
Fast
V_CC = 1.7 V − 3.6 V
Fast−Plus
V_CC = 2.2 V − 3.6 V
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
F_SCL (Note 5) Clock Frequency
10
100
10
400
10
1,000
kHz
t_HD:STA
START Condition Hold Time
4
0.6
0.26
ms
t_LOW
Low Period of SCL Clock
4.7
1.3
0.50
ms
t_HIGH
High Period of SCL Clock
4
0.6
0.26
ms
t_SU:STA
START Condition Setup Time
4.7
0.6
0.26
ms
t_HD:DI
Data In Hold Time
0
0
0
ms
t_SU:DAT
Data In Setup Time
250
100
50
ns
t_R (Note 7)
SDA and SCL Rise Time
1,000
300
120
ns
t_F (Note 7)
SDA and SCL Fall Time
300
300
120
ns
t_SU:STO
STOP Condition Setup Time
4
0.6
0.26
ms
t_BUF
Bus Free Time Between
4.7
1.3
0.5
ms
STOP and START
t_HD:DAT
Data Out Hold Time
200
3450
200
900
0
350
ns
T_i (Note 7)
Noise Pulse Filtered at SCL
50
50
50
ns
and SDA Inputs
t_SU:WP
WP Setup Time
0
0
0
ms
t_HD:WP
WP Hold Time
2.5
2.5
1
ms
t_WR
Write Cycle Time
4
4
4
ms
t_INIT (Notes 7, 8) Power-up to Ready Mode
0.5
0.5
0.5
ms
t_POFF (Note 9) Warm power cycle off time
0.2
0.2
0.2
ms
t_TIMEOUT (Note 10) Detect clock low timeout
25
35
25
35
25
35
ms
5. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is limited only by the SMBus
time−out. The device also meets the Fast and Standard I²C specifications, except that T_i and t_DH are shorter, as required by the 1 MHz Fast
Plus protocol.
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t_INIT is the delay between the Power−On Reset threshold (V_POR+) and the device is ready to accept commands.
9. Power−Off delay to ensure a proper Reset when the V_CC drops below V_POR−
10. A timeout condition can only be ensured if SCL is driven low for t_TIMEOUT(Max) or longer; then, N34C04 is reset and ready to receive a new
START condition. N34C04 does not reset if SCL is driven low for less than t_TIMEOUT(Min). The interface will reset itself and will release the
SDA line if the SCL line stays low beyond the t_TIMEOUT limit. The time−out count takes place when SCL is low in the time interval between
START and STOP.
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x V_CC to 0.8 x V_CC
≤ 50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x V_CC, 0.7 x V_CC
0.3 x V_CC, 0.7 x V_CC
Current Source: I_OL = 6 mA; C_L = 100 pF
Table 7. PIN CAPACITANCE (T_A = 25°C, V_CC = 3.6 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments
Min
Max
Unit
C_IN
SDA, Pin Capacitance
Input Capacitance (other pins)
V_IN = 0
V_IN = 0
8
pF
6
pF
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