N34C04 Datasheet, PDF (6/11 Pages) ON Semiconductor – 4-Kb Serial SPD EEPROM for DDR4 DIMM

N34C04
EEPROM Bank Selection
Upon power−up, the address pointer is initialized to 00h
pointing to the first location in the lower 2−Kb bank (SPD
page 0).
Only one SPD page is visible (active) at any given time.
The lower SPD page is automatically selected at power−up.
The upper SPD page can be activated (and the lower one
implicitly de−activated) by executing the SPA1 utility
command. The SPA0 utility command can then be used to
re−activate the lower SPD page without powering down.
The identity of the active SPD page can be retrieved with the
RPA command.
SPD page selection related command details are
presented in Table 11c, Table 11d, Figure 12 and Figure 13.
Write Operations
EEPROM Byte Write
To write data to the EEPROM, the Master creates a
START condition on the bus, and then sends out the
appropriate Slave address (with the R/W bit set to ‘0’),
followed by a starting data byte address, followed by data.
The matching Slave will acknowledge the Slave address,
EEPROM byte address and the data byte (Figure 5). The
Master then ends the session by creating a STOP condition
on the bus. The STOP starts the internal Write cycle for the
(non−volatile) EEPROM data (Figure 6).
EEPROM Page Write
Each of the two 2−Kb banks is organized as 16 pages of
16 bytes each (not to be confused with the SPD page, which
refers to the entire 2−Kb bank). One of the 16 memory pages
is selected by the 4 most significant bits of the byte address,
while the 4 least significant bits point to the byte position
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 7).
During data load, the internal byte position pointer is
automatically incremented after each data byte is loaded. If
the Master transmits more than 16 data bytes, then earlier
data will be replaced by later data in a ‘wrap−around’
fashion within the 16−byte wide data buffer. The internal
Write cycle then starts following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
N34C04 is busy writing to EEPROM, or is ready to accept
commands. Polling is executed by interrogating the device
with a ‘Selective Read’ command (see READ
OPERATIONS). The N34C04 will not acknowledge the
Slave address as long as internal EEPROM Write is in
progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the N34C04. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 8). If the WP pin is HIGH during the strobe
interval, the N34C04 will not acknowledge the data byte and
the Write request will be rejected.
Delivery State
The N34C04 is shipped ‘unprotected’, i.e. none of the
Software Write Protection (SWP) flags is set. The entire
memory is erased, i.e. all bytes are 0xFF.
Read Operations
Immediate Read
A N34C04 presented with a Slave address containing a ‘1’
in the R/W position will acknowledge the Slave address and
will then start transmitting EEPROM data from the current
address pointer location. The Master stops this transmission
by responding with NoACK, followed by a STOP
(Figure 9).
Selective Read
The Read operation can be started from a specific address,
by preceding the Immediate Read sequence with a ‘data less’
Write sequence. The Master sends out a START, Slave
address and byte address, but rather than following up with
data (as in a Write operation), the Master then issues another
START and continuous with an Immediate Read sequence
(Figure 10).
Sequential EEPROM Read
EEPROM data can be read out indefinitely, as long as the
Master responds with ACK (Figure 11). The internal address
pointer is automatically incremented after every data byte
sent to the bus. If the end of the active 2−Kb bank is reached
during continuous Read, then the address count
‘wraps−around’ to the beginning of the active 2−Kb bank,
etc. Sequential Read works with either Immediate Read or
Selective Read, the only difference being that in the latter
case the starting address is intentionally updated.
BUS ACTIVITY: S
T
A
MASTER ^R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
SDA LINE S
P
SLAVE
A
A
A
C
C
C
K
K
K
Figure 5. EEPROM Byte Write
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