N34C04 Datasheet, PDF (8/11 Pages) ON Semiconductor – 4-Kb Serial SPD EEPROM for DDR4 DIMM

N34C04
BUS ACTIVITY: S
S
N
T
T
OS
A
MASTER R
SLAVE
ADDRESS
BYTE
A _SLAVE
ADDRESS (n) ^R ADDRESS
AT
CO
T
T
KP
SDA LINE S
S
P
SLAVE
A
A
C
C
K
K
A
C ^{DATA n}
K
Figure 10. EEPROM Selective Read
BUS ACTIVITY:
SLAVE
MASTER ADDRESS
SDA LINE
A
SLAVE
C
K
A
A
A
C
C
C
K
K
K
DATA n
DATA n+1
DATA n+2
Figure 11. EEPROM Sequential Read
N
OS
AT
CO
KP
P
DATA n+x
Software Write Protection
Each 1−Kb memory block can be individually protected
against Write requests. Block identities are:
Block 0: byte address 0x00...0x7F (SPD page address = 0)
Block 1: byte address 0x80...0xFF (SPD page address = 0)
Block 2: byte address 0x00...0x7F (SPD page address = 1)
Block 3: byte address 0x80...0xFF (SPD page address = 1)
Block Software Write Protection (SWP) flags can be set
or cleared in the presence of a very high voltage V_HV on
address pin A0. The V_HV condition must be established on
pin A0 before the START and maintained just beyond the
STOP. The D.C. OPERATING CONDITIONS for SWP
operations are shown in Table 10.
SWP command details are listed in Tables 11a and 11b.
SWP Slave addresses follow the standard I²C convention,
i.e. to read the state of a SWP flag, the LSB of the Slave
address must be ‘1’, and to set or clear a flag, it must be ‘0’.
For Set/Clear commands a dummy byte address and dummy
data byte must be provided (Figure 12). In contrast to a
regular memory Read, a SWP Read does not return data.
Instead the N34C04 will respond with NoACK if the flag is
set and with ACK if the flag is not set (Figure 13).
Table 10. SWPn AND CWP D.C. OPERATION CONDITION
Symbol
Parameter
Test Conditions
DV_HV
I_HVD
V_HV
A₀ Overdrive (V_HV − V_CC)
A₀ High Voltage Detector Current
A₀ Very High Voltage
1.7 V < V_CC < 3.6 V
Min
Max
Units
4.8
V
0.1
mA
7
10
V
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