BUD42D Datasheet, PDF (9/14 Pages) ON Semiconductor – High Speed, High Gain Bipolar NPN Transistor with Antisaturation Network and Transient Voltage Suppression Capability

10
5 ms
1 ms
dc
1
BUD42D
MAXIMUM RATINGS
5
10 ms ^{1 ms}
4
3
T_J = 125°C
GAIN ≥ 4
L_C = 500 mH
0.1
0.01
10
100
1000
V_CE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 28. Forward Bias Safe Operating Area
2
1
V_BE(off) = −5 V
0
V_BE = 0 V V_BE(off) = −1.5 V
300
400
500
600
700
V_CE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 29. Reverse Bias Safe Operating Area
1
0.8
SECOND BREAKDOWN
DERATING
0.6
0.4
0.2
0
20 40
THERMAL DERATING
60
80 100 120 140 160
T_C, CASE TEMPERATURE (°C)
Figure 30. Power Derating
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I_C−V_CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate. The data of Figure 28 is
based on T_C = 25°C; T_j(pk) is variable depending on power
level. Second breakdown pulse limits are valid for duty
cycles to 10% but must be derated when T_C > 25°C. Second
Breakdown limitations do not derate like thermal
limitations. Allowable current at the voltages shown on
Figure 28 may be found at any case temperature by using the
appropriate curve on Figure 30.
T_j(pk) may be calculated from the data in Figure 31. At any
case temperatures, thermal limitations will reduce the power
that can be handled to values less than the limitations
imposed by second breakdown. For inductive loads, high
voltage and current must be sustained simultaneously during
turn−off with the base to emitter junction reverse biased. The
safe level is specified as reverse biased safe operating area
(Figure 29). This rating is verified under clamped conditions
so that the device is never subjected to an avalanche mode.
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