Q32M210 Datasheet, PDF (8/50 Pages) ON Semiconductor – Precision Mixed-Signal 32-bit Microcontroller SPI/SQI interface.

Q32M210
The PWM On/Off duty cycle time can be configured by the
application allowing the MSWs to act as a power regulator.
ARM Cortex−M3 Processor
The ARM Cortex−M3 processor is a 32−bit RISC
controller specifically designed to meet the needs of
advanced, high−performance, low−power applications. The
ARM Cortex−M3 processor provides outstanding
computational performance and exceptional system
response to interrupts while providing small core footprint,
industry leading code density enabling smaller memories,
reduced pin count and low power consumption.
The Q32M210 implementation of the ARM Cortex−M3
Processor contains all necessary peripherals and bus
systems to provide a complete device optimized for battery
powered sensor interface applications.
Memories
Flash Memory
256 kB flash is available for storage of application code
and data. Flash memory can be written one or more words
at a time. Each page must be erased between writes to a flash
word. The flash memory can be erased as a set all at once or
in individual 2 kB pages. An additional reserved block of
flash memory is used to store factory calibration information
provided by ON Semiconductor. This block can not be
written by the application.
The ARM Cortex−M3 processor executes application
code directly from flash with zero wait states.
Flash Error Checking and Correction
A dedicated hardware block performs real−time error
checking and correction of the flash. Additional parity bits
are stored automatically for each word in the flash. The
hardware ECC is able to detect up to 2−bit errors per word
or detect and correct 1−bit error per word. The hardware
ECC operates as each word is read from the flash. An
interrupt can be generated upon correction of a bit error and
a bus fault will be generated when a bit error is detected, but
cannot be corrected.
SRAM
48 kB of low−power SRAM is available for storage of
intermediate data as well as application code.
ROM
An on−chip ROM includes boot functionality as well as
firmware routines supporting writing to flash in an
application.
External Interrupt Controller
Eight configurable external interrupt sources may be
connected to any eight GPIO pins on the device. This is in
addition to a dedicated interrupt for the wakeup controller.
Each interrupt may be individually configured for positive
edge triggering, negative edge triggering, high level
triggering, or low level triggering.
A dedicated non−maskable interrupt (NMI) pin is
connected directly to the ARM Cortex−M3 Processor. A
logic high level on this pin will trigger the interrupt handler
for the NMI.
DMA
A flexible DMA unit supports low overhead data
exchange between system blocks. Memory−to−Peripheral,
Peripheral−to−Memory, and Memory−to−Memory modes
are available. Four simultaneous DMA channels can be
established with configurable sources and sinks.
The DMA can be used with the UART, SPI, SQI, I²C,
USB, and PCM interfaces, as well as the ADCs and DACs.
The DMA operates in the background allowing the ARM
Cortex−M3 Processor to execute other applications or to
reduce its operating frequency to conserve power.
General−Purpose Timers
The device contains four general−purpose timers. Each
timer features a 12−bit countdown mode, an external
interrupt to the ARM Cortex−M3 Processor, a dedicated
prescaler, and the ability to poll the counter value. These four
general−purpose timers are in addition to the 24−bit
SYSTICK timer included as part of the ARM Cortex−M3
Processor.
CRC Engine
A 16−bit hardware CRC engine is available. The CRC
engine may be used to ensure data integrity of application
code and data. The CRC engine’s input port and output port
are directly accessible from the ARM Cortex−M3 Processor.
The starting vector may be set to any value. Subsequently,
data words of multiple bit lengths can be added to the CRC.
The 16−bit CRC−CCITT polynomial is used.
Watchdog Timer
The device contains a digital watchdog timer. The
watchdog timer is intended to prevent an indefinite system
hang when an application error occurs. The application must
periodically refresh the watchdog counter during operation.
If a watchdog timeout occurs an initial alert interrupt is
generated. If a subsequent watchdog timeout occurs, a
system reset is generated. The initial alert may be used to
gracefully shut down the system.
Dual UART
Two general−purpose UART interfaces are available. The
UARTs support the standard RS232 protocol and baud rates
at the VDDIO0 voltage level. The UART format is fixed at
one start bit, eight data bits, and one stop bit. The baud rate
is configurable over a wide range of baud rates up to
250 kbaud using a 1 MHz source clock.
The UART interfaces may be used either directly from the
ARM Cortex−M3 Processor or through the DMA
Controller.
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