Q32M210 Datasheet, PDF (42/50 Pages) ON Semiconductor – Precision Mixed-Signal 32-bit Microcontroller SPI/SQI interface.

Q32M210
1. 2’s Complement – A 0 V input corresponds to
0x8000, and a maximum input results in 0x7FFF.
2. Unsigned – A 0 V input corresponds to 0x0000,
and a maximum input results in 0xFFFF.
The nominal ADC data rate is 1000 samples/second for a
system clock of 3.0 MHz and an MCLK divisor of 1. The
ADC sampling is periodic. Samples are provided at the same
period regardless of the voltage level. Faster data rates are
obtained by reconfiguring the ADC clock and configuration.
Lower data rates are obtained through decimation of the
base rate. The hardware−based decimation filters are
implemented using cascaded, programmable low−pass
filters of variable length. This architecture enables the
application to sample data at any desired rate including rates
down to 10 samples/second. The filters are designed to
provide more than 100 dB rejection of common line
frequencies (50/60 Hz) at this rate.
Reducing the ADC data rate through the decimation filter
provides an increase in the Signal−to−Noise ratio by
reducing the number of noise bits. This results in an increase
in the signal dynamic range.
Triple DACs
Reconfiguring the ADC clock to obtain faster data rates
requires careful selection of the PGA AAF capacitor to
ensure adequate filtering and signal bandwidth.
The PGA + ADC feature low gain and offset temperature
drifts making them ideal for systems where calibration may
be performed at a single known temperature but the
operating condition may vary. The digital output of the ADC
is connected to a hardware gain and offset correction unit.
The absolute gain and offset of the signal chain may be
calibrated using external known voltages or voltages based
on VREF. The calibration factors are configured in the gain
and offset correction unit. All subsequent samples are
automatically adjusted by these factors.
PGA0 includes a voltage detect comparator with
programmable thresholds. When the comparator is enabled
a signal is provided to the ARM Cortex−M3 Processor that
indicates when the PGA0 output voltage exceeds the
threshold. The application may use the signal to enable the
ADC or other system blocks to perform a sensor
measurement. This results in lower overall current
consumption since the ADC may be disabled while waiting
for a specific voltage level to occur.
3 x VREF
2 x VREF
VREF
Ref Select
DAC0
DAC0
2 x VREF
DAC0
Code
DAC1
DAC2
DAC1
VBATA
2 x VREF
Buffer
DAC2
VSS
Figure 28. Triple DACs
DAC1
Code
DAC2
Code
Three Digital−to−Analog Converters (DACs) are
available. Each DAC is implemented using a current
steering network to minimum power consumption. The
DACs have 10−bits of resolution. The reference voltage is
selectable on DAC0 and fixed on DAC1 and DAC2. The
effective voltage per LSB is determined by the reference
voltage. The DAC outputs are buffered to ensure sufficient
drive capability of the reference terminal of the on−chip
opamps and auxiliary analog inputs.
DAC0 provides the highest level of reference voltage
flexibility by allowing the dynamic range of the converter to
be mapped into three ranges: 1 x VREF, 2 x VREF, and 3 x
VREF. The first range, VREF, provides maximum voltage
resolution per LSB. The second range, 2 x VREF, provides
a compromise between resolution per LSB and output
voltage range. The third range, 3 x VREF, provides a lowest
resolution per LSB but the largest output range.
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