Q32M210 Datasheet, PDF (6/50 Pages) ON Semiconductor – Precision Mixed-Signal 32-bit Microcontroller SPI/SQI interface.

Q32M210
Clocking
The device contains several clock generators and clock
I/O capability. After Power−on Reset, the device selects the
internal oscillator as the system clock source. The default
clock frequency at POR is 3 MHz. After boot, the
application may select another frequency or switch to
another clock source. The device may select the real−time
crystal oscillator (32.768 kHz) as the clock source, when
low operating frequencies are required to save power.
Internal Oscillator
The device contains a reconfigurable, factory calibrated
internal oscillator. The calibration settings are stored in the
on−chip flash. Settings are available for all integer
frequencies in the normal operating range (1 MHz to
16 MHz). Finer calibration is possible.
The default setting after Power−on Reset is 3 MHz. The
application can switch to any operating frequency after
entering run mode.
External Clock
The device contains an external clock I/O pin
(EXT_CLK). EXT_CLK may be used as a clock source for
the entire system or as a clock output. The application may
switch to use an externally supplied clock or output a clock
after boot. If neither function is desired EXT_CLK may be
left floating.
An external clock detection circuit is included that will
automatically switch the system to the internal oscillator, if
the external clock is selected, but no clock signal is detected.
When EXT_CLK is used as an output, the frequency of
the output clock can be divided before EXT_CLK is output.
Real−Time Clock
The device contains an ultra low−power real−time clock
(RTC). The RTC includes a real−time crystal oscillator,
read−write RTC counters, and a configurable alarm. The
real−time crystal oscillator utilizes a 32.768 kHz external
crystal.
The RTC may be enabled or disabled in each of the three
operating modes. The RTC is powered directly from VBAT.
This allows the RTC to continue to run when the VDDD
Digital Supply Regulator voltage is reduced in standby
mode or disabled in sleep mode and thus the system date and
time information are always maintained. The RTC is reset
after the initial Power−on Reset but remains operational
through a digital reset (RSTB or watchdog) and operating
mode switching.
The alarm function can be configured to wake−up the
system from standby mode or sleep mode at a
pre−determined time. The alarm will also generate an
interrupt to the ARM Cortex−M3 Processor. The alarm can
be configured for absolute mode or relative mode. In relative
mode, the alarm is automatically reloaded after each alarm
trigger. This is useful for extremely low−duty−cycle
applications that require periodic polling.
USB Crystal Oscillator
The device contains a dedicated USB crystal oscillator.
The oscillator requires an external 48 MHz crystal for
compliance with the USB interface specification. The clock
output is used internally for the USB PHY and USB core.
During USB operation the ARM Cortex−M3 Processor
and all other system blocks continue to run on the slower
system clock. This allows the device to achieve low system
current even while the USB interface is active.
The USB Crystal Oscillator can be enabled or disabled.
Clock Divisors
On−chip clock divisors and prescalers are available to
provide selectable frequencies to the ARM Cortex−M3
Processor, sensor interface, peripherals and external
interfaces. These divided clocks are derived from the root
clock source and may be configured independently. This
adjustability allows the optimum clock frequency to be
selected for each system component.
Sensor Interface
Opamps
Three uncommitted low−noise opamps are available.
Each opamp is directly powered from the VBATA supply for
achieving high input dynamic range for sensor interface
signals. Each of the opamp’s positive and negative terminals
is brought out to a dedicated input pin on the device. Each
opamp output terminal is connected to two dedicated output
pins. An internal switch selects between output to one or
both of the output pins, allowing for dynamic
reconfigurability of the external opamp feedback network.
Signal Multiplexing
A comprehensive input multiplexing scheme allows for
flexible interconnection of a wide range of sensors and
external circuits to be connected to the sensor interface. The
input multiplexing consists of:
• An 8:1 analog multiplexer – Connects one of 8
low−leakage input pins to an opamp negative terminal
• A 3:1 analog multiplexer – Connects one of 3
low−leakage input pins to an alternate sensor node
(ALT0) and optionally to an opamp negative terminal
• A 5:1 analog multiplexer – Connects one of 5
low−leakage input pins to an alternate sensor node
(ALT1) and optionally to an opamp negative terminal
Each multiplexer signal path features low Ron
characteristics providing nearly transparent signal routing
for any external sensor. The input multiplexer configuration
may be changed on−the−fly by the application.
Dual PGA and ADC
Two independent 16−bit Analog−to−Digital Converters
(ADCs) are available. The ADCs provide a very high
resolution, a high degree of linearity, as well as low gain and
offset temperature drifts. Each ADC is coupled with a
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