AMIS-30622_13 Datasheet, PDF (8/50 Pages) ON Semiconductor – I2C Micro-Stepping Motor Driver

AMIS−30622
AC PARAMETERS
The AC parameters are guaranteed for temperature and V_BB in the operating range unless otherwise specified.
Table 6. AC PARAMETERS
Symbol Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
POWERUP
T_pu
Power−up time
INTERNAL OSCILLATOR
Guaranteed by design
10
ms
f_osc
Frequency of internal oscillator
I²C TRANSCEIVER (STANDARD MODE)
V_BB = 14 V
3.6
4.0
4.4
MHz
f_SCL
t_HD,START
SCL clock frequency
Hold time (repeated) START condition. After
this period the first clock pulse is generated.
100
kHz
4.0
ms
t_LOW
t_HIGH
t_SU,START
t_HD,DATA
SDA
SCK
LOW period of the SCK clock
HIGH period of the SCK clock
Set−up time for a repeated START condition
Data hold time for I²C bus devices
4.7
4.0
4.7
0
(Note 16)
ms
ms
ms
3.45
ms
(Note 17)
t_SU,DATA
t_R
t_F
t_SU,STOP
t_BUF
Data set−up time
Rise time of SDA and SCK signals
Fall time of SDA and SCK signals
Set−up time for STOP condition
Bus free time between STOP and START
condition
250
ns
1.0
ms
0.3
ms
4.0
ms
4.7
ms
I²C TRANSCEIVER (FAST MODE)
f_SCL
t_HD,START
SCL clock frequency
Hold time (repeated) START condition. After
this period the first clock pulse is generated.
360
kHz
0.6
ms
t_LOW
t_HIGH
t_SU,START
t_HD,DATA
t_SU,DATA
SDA
SCK
LOW period of the SCK clock
HIGH period of the SCK clock
Set−up time for a repeated START condition
Data hold time for I²C bus devices
Data set−up time
1.3
0.6
0.6
0
(Note 16)
100
(Note 18)
ms
ms
ms
0.9
ms
(Note 17)
ns
t_R
t_F
t_SU,STOP
t_BUF
Rise time of SDA and SCK signals
Fall time of SDA and SCK signals
Set−up time for STOP condition
Bus free time between STOP and START
condition
20 +
0.1 C_B
20 +
0.1 C_B
0.6
1.3
300
ns
300
ns
ms
ms
15. The maximum number of connected I²C devices is dependent on the number of available addresses and the maximum bus capacitance
to still guarantee the rise and fall times of the bus signals.
16. An I²C device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
17. The maximum t_HD,DAT has only to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.
18. A Fast−mode I²C−bus device can be used in a standard−mode I²C bus system, but the requirement t_SU,DATA w 250 ns must than be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line trmax + t_SU,DATA = 1000 + 250 = 1250 ns (according to the
standard−mode I²C−bus specification) before the SCL line is released.
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