AMIS-30622_13 Datasheet, PDF (37/50 Pages) ON Semiconductor – I2C Micro-Stepping Motor Driver

AMIS−30622
Transferring Data
Byte Format
Every byte put on the SDA line must be 8−bits long. The
number of bytes that can be transmitted per transfer to
AMIS−30622 is restricted to eight. Each byte has to be
followed by an acknowledge bit. Data is transferred with the
SDA
START
most significant bit (MSB) first (See Figure 25). If a slave
can’t receive or transmit another complete byte of data, it can
hold the clock line SCK LOW to force the master into a wait
state. Data transfer then continues when the slave is ready for
another byte of data and releases clock line SCK.
STOP
SCK
MSB
Acknowledgement
signal from slave
Clock line held
low by slave
1
2
START
condition
7
8
9
Aknowledge related
clock puse from master
1
2
3−8
9
ACK
STOP
condition
Figure 25. Data Transfer on the I²C−bus
Acknowledge
Data transfer with acknowledge is obligatory. The
acknowledge−related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the acknowledge clock pulse so that it
remains stable LOW during the HIGH period of this clock
pulse (see Figure 26). Of course, set−up and hold times must
also taken into account (see Table 6). When AMIS−30622
doesn’t acknowledge the slave address, the data line will be
left HIGH. The master can than generate either a STOP
condition to abort the transfer, or a repeated START
condition to start a new transfer.
If AMIS−30622 as slave−receiver does acknowledge the
slave address but later in the transfer cannot receive any
more data bytes, this is indicated by generating a
not−acknowledge on the first byte to follow. The master
generates than a STOP or a repeated START condition.
If a master−receiver is involved in the transfer, it must
signal the end of data to the slave−transmitter by not
generating an acknowledge on the last byte that was clocked
out of the slave. AMIS−30622 as slave−transmitter shall
release the data line to allow the master to generate STOP or
repeated START condition.
SDA by master
transmitter
START
Master releases the Data line
MSB
SDA by slave
receiver
Not acknowledged
SCK from
master
1
START
condition
Acknowledged
2
8
Slave pulls data line
low if Acknowledged
9
Aknowledge related
clock puse from master
Figure 26. Acknowledge on the I²C−bus
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