XOCLCC6EVB Datasheet, PDF (7/9 Pages) ON Semiconductor – Crystal Clock Oscillator Module Evaluation Board Manual for NBX Family

XOCLCC6EVB
Evaluation Board Fabrication Notes
1. MATERIAL: FR−4
2. FINISHED COPPER TO BE loz. (0.0014) EXTERNAL LAYERS
3. MINIMUM COPPER PLATING 0.0007” THICK FOR PLATED THRU HOLES ANNULAR RING TO BE 0.0002”
MINIMUM
4. LPI SOLDERMASK GREEN
5. SOLDERMASK REGISTRATION "0.002” N/A
6. ALL EXPOSED COPPER AREAS TO BE GOLD PLATED (0.000030” GOLD OVER 0.000100” NICKEL)
7. IF SPECIFIED, SILKSCREEN IS TO BE WHITE EPOXY INK.
8. HOLE DIAMETER TOLERANCE IS "0.002”, MAXIMUM LAYER TO LAYER MISREGISTRATION SHALL
BE 0.004”, MEASUREMENT METHOD MUST COMPLY WITH MIL−P−55110D, FIGURE 1.
9. FINISHED CONDUCTOR WIDTH SHALL NOT VARY MORE THAN "0.001” FROM ARTWORK MASTER
50 W TRACES ARE 0.024” WIDE.
10. WARP AND TWIST OF SINGLE SIDED BOARDS SHALL NOT EXCEED 0.002”PER INCH, WARP AND
TWIST OF MULTI−LAYER BOARDS SHALL NOT EXCEED 0.010” PER INCH.
11. ALL DIMENTIONS ARE IN INCHES UNLESS OTHERWISE SPECIFIED TOLERANCES. XX "0.010” XXX
"0.004”.
12. ACCEPTABILITY REQUIREMENTS PER IPC−A−600E.
13. DRAWING IS VIEWED FROM COMPONENT OR PRIMARY SIDE.
14. THIS IS A 4 LAYER BOARD.
15. ALL HOLES ARE PLATED THRU UNLESS OTHERWISE SPECIFIED.
16. DRILL SIZE UNITS ARE THOUSANDTHS OF AN INCH.
17. TRIM ALL SILKSCREEN WHICH FLOWS OVER VIA HOLES OR SMD PADS.
18. BREAK ALL SHARP EDGES, PCB EDGES SHOULD BE SMOOTH AND EVEN.
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