XOCLCC6EVB Datasheet, PDF (4/9 Pages) ON Semiconductor – Crystal Clock Oscillator Module Evaluation Board Manual for NBX Family

XOCLCC6EVB
LVDS: Driver termination is a 100 W resistor across the
differential lines located at the receiver input.
Table 4. TYPICAL LAB SETUP
LOGIC Levels
LVPECL
CML
LVDS
Power Supply
Split 3.3 V
Single −3.3 V
Single 3.3 V
Typical Lab
Setup
See Figure 4
See Figure 5
See Figure 6
Step 3: Configure FSEL and OE
The FSEL and OE control pins can be controlled from an
external source via the appropriate test point, or via the
jumper headers located on the evaluation board, as indicated
in Figures 2 and 7. Refer to the specific device datasheet for
details on the proper settings for these pins.
VDD = +2.0V
+
+2.0V
−
Power Supply
+2.0V
HL
OE
HL
VDD
J1
Digital Oscilloscope
Or Frequency Counter
50W
+
FSEL
J2
+1.3V
SMAGND
C3
50W
−
C4
DUTGND
VEE = −1.3
−1.3
0V
Figure 4. Split Power Supply Lab Setup for LVPECL Outputs (DO NOT JUMPER DUTGND and SMAGND)
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