XOCLCC6EVB Datasheet, PDF (5/9 Pages) ON Semiconductor – Crystal Clock Oscillator Module Evaluation Board Manual for NBX Family

0V
VDD = SMAGND = 0V
+
0V
−
Power Supply
XOCLCC6EVB
0V
HL
OE
HL
VDD
J1
Digital Oscilloscope
Or Frequency Counter
50W
+
FSEL
J2
−3.3V
SMAGND
C3
50W
−
C4
DUTGND
VEE = −3.3V
0V
−3.3V
Note: For CML outputs, 50 W to V_DD is needed for proper termination. See application note AND8173/D.
Figure 5. Typical Lab Setup for CML Outputs (DO NOT JUMPER DUTGND and SMAGND)
+3.3V
Power Supply
+
+3.3V
−
HL
VDD
Jumper
OE
HL
J1
100W
FSEL
J2
SMAGND _C3
C4
DUTGND
High Impedance
Differential
Probe
Digital Oscilloscope
0V
Figure 6. Typical Lab Setup for LVDS Outputs (JUMPER DUTGND and SMAGND)
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