XOCLCC6EVB Datasheet, PDF (3/9 Pages) ON Semiconductor – Crystal Clock Oscillator Module Evaluation Board Manual for NBX Family

XOCLCC6EVB
Evaluation Board Jumper Headers on OE (Pin 4), FSEL (Pin 5)
Evaluation Board Jumper Header on DUTGND (Pin 3)
Figure 3. Select Positions for Evaluation Board Jumper Headers on OE (Pin 4), FSEL (Pin 5), and DUTGND (Pin 3)
TIME DOMAIN MEASUREMENTS
Equipment
Table 2 indicates the recommended equipment for
making characterization and performance measurements.
Table 2. BASIC EQUIPMENT
Description
Example Equipment
Qty
Power Supply with 4
HP6624A or similar
1
outputs
Real−Time Oscilloscope DPO70804 or similar
1
Matched High Speed
Storm, Semflex, or
2
Cables with SMA
similar
Connectors
Power supply cables
4
Setup
The following steps should be followed for proper
equipment setup.
Step 1: Connect Power (split power supply mode)
Three power levels must be provided to the board: V_DD,
DUTGND, and SMAGND via the test point anvils at the
edges of the board. Bypass capacitors are installed from
V_DD to SMAGND and DUTGND to SMAGND near the test
points (see BOM). Devices may be tested in one of three
supply modes (see Table 3):
A). Single (Positive) +3.3 V Setup
No offset to supplies or output levels
B). Split 3.3 V Setup
Offsets the V_DD, DUTGND, and output voltage levels by
−1.3 V and avoids an additional, separate V_TT supply and
allows a direct connection to test equipment such as an
oscilloscope or counter with 50 W impedance to GND
inputs. SMAGND = V_TT = V_DD – 2.0 V = 0.0 V.
C). Single (Negative) −3.3 V Setup
Offsets the V_DD, DUTGND, and output voltage levels by
−3.3 V
Table 3. XOCLCC6EVB POWER SUPPLY
CONNECTION VOLTAGES
A). Single
Positive
+3.3 V Setup
B). Split 3.3 V
Setup
C). Single
Negative
−3.3 V Setup
V_DD = 3.3 V
V_TT
= V_DD − 2.0 V
= 1.3 V
DUTGND
= SMAGND
=0V
V_DD = 2.0 V
V_TT
= V_DD − 2.0 V
= SMAGND
=0V
DUTGND
= −1.3 V
V_DD = 0 V
V_TT
= V_DD − 2.0 V
= −2.0 V SMAGND
= V_DD = 0 V
DUTGND = −3.3 V
NOTE: SMAGND is the SMA cable shield reference for
the inputs and outputs only, not to be confused
with the device ground pin (DUTGND).
Step 2: Connect Output Signals
Table 4 gives a list of specific LOGIC Levels and their
appropriate Power Supply and Typical Lab Setup
conditions
LVPECL: The LVPECL outputs have standard, open
emitter outputs and must be externally DC loaded and AC
terminated. A split power supply technique takes advantage
of terminating the LVPECL outputs into 50 W of an
oscilloscope or a frequency counter. Since V_TT = V_DD – 2 V,
offsetting V_DD to +2.0 V yields V_TT = 0 V or Ground
(SMAGND). The V_TT terminal connects to the isolated
SMAGND connector ground plane, and is not to be
confused with the device ground pin (DUTGND). (See
Application Note AN8020/D for details on ECL
termination).
CML: For CML lab setup and test, operation with
negative supply voltage is recommended to enable the 50 W
internal impedance in the oscilloscope to be used as a
termination of the CML signals (V_DD = 0.0 V, SMAGND =
0.0 V, and DUTGND = −3.3 V (See Application Note
AN8173/D for details on CML termination).
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