AMIS-30523 Datasheet, PDF (27/35 Pages) ON Semiconductor – CAN Micro-Stepping Motor Driver

AMIS−30523
Table 13. WATCHDOG TIMEOUT INTERVAL AS
FUNCTION OF WDT[3.0]
Index
WDT[3:0]
0
0000
t_WDTO (ms)
32
1
0001
64
2
0010
96
3
0011
128
4
0100
160
5
0101
192
6
0110
224
7
0111
256
8
1000
288
9
1001
320
A
1010
352
B
1011
384
C
1100
416
D
1101
448
E
1110
480
F
1111
512
CLR Pin (= Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMIS−30523, the input
CLR needs to be pulled to logic 1 during minimum time
given by t_CLR. (See Table 6 AC Parameters Motor Driver).
This reset function clears all internal registers without the
need of a power−cycle, except in sleep mode. The operation
of all analog circuits is depending on the reset state of the
digital, charge pump remains active. Logic 0 on CLR pin
resumes normal operation again.
The voltage regulator remains functional during and after
the reset and the PORB/WD pin is not activated. Watchdog
function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 (See Table 14
SPI Control Registers address 03h) is provided to enter a
so−called “sleep mode”. This mode allows reduction of
current−consumption when the motor is not in operation.
The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current
increase during SPI communication)
• Oscillator and digital clocks are silent, except during
SPI communication
The voltage regulator remains active but with reduced
current−output capability (I_LOADSLP). The watchdog timer
stops running and it’s value is kept in the counter. Upon
leaving sleep mode, this timer continues from the value it
had before entering sleep mode.
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A start−up time is needed for the charge pump to
stabilize. After this time, (tcpu) NXT commands can be
issued.
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