SCY99091FCT2G Datasheet, PDF(21/26 Page) ON Semiconductor – Voltage Detector Series with Programmable Delay

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SCY99091FCT2G Datasheet, PDF (21/26 Pages) ON Semiconductor – Voltage Detector Series with Programmable Delay

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Power Supply 1

(System Core)

3.3 V Power Supply 2

(I/O Subsystem)

5.0 V Power Supply 3

(Peripheral Subsystem)

NCP302, NCP303

R1 is Optional CD Pin Pullup

2 Input

NCP302L

Series

3 GND

* RP

Reset Output

*Required for

NCP303

To MCU or

Logic Circuitry

2 Input

NCP301

LSN30T1

Reset Output

3 GND

2 Input

NCP301

LSN45T1

Reset Output

3 GND

VIN

Power Supply 1

Power Supply 2

Power Supply 3

CD Pin

VTVCIDN

NCP302L

RESET Output

Note: VTCD 0.675 * VIN

tD2

Figure 46. MultiâRail Supply Undervoltage Monitor with Power Good

This circuit monitors multiple power supply rails for

undervoltage conditions. If any of the three power supplies

are in an undervoltage condition, the NCP302 reset output

will be immediately set to an active low level. All three

power supplies must be above their minimum voltage levels

for the NCP302 reset output to generate a âPower Goodâ

level (Reset Output = Power Supply 1 or VP).

Optionally, R1 may be added to provide a smaller

effective CD pin pullup resistance, (RDâ), where

RDâ = R1 || RD, with RD (internal CD pin pullup resistance)

approximately equal to 1.0 MW, and R1 > 5 kW. If R1 << RD,

then R1 also can decrease the reset output delay time (tD2)

variance over the operating temperature range.

The Power Good signal time delay (tD2) can be estimated

by: tD2 â RD * CD, with RD in Ohms, and CD in Farads. If

R1 is installed, then RDâ is substituted for RD. RP is added

only if using the NCP303 to replace the NCP302. This

allows the Reset Output to be pulled up to VP, which can be

the Power Supply 1 or an independent power supply rail.

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