SCY99091FCT2G Datasheet, PDF(20/26 Page) ON Semiconductor – Voltage Detector Series with Programmable Delay

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SCY99091FCT2G Datasheet, PDF (20/26 Pages) ON Semiconductor – Voltage Detector Series with Programmable Delay

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Logic 1

NCP302, NCP303

VDD

2 Input

NCP302L

Series

Reset Output

3 GND

To MCU or

Logic Circuitry

NCP302

Input Pin

Logic 1

Enable

CD Pin

VDD

VDET

VDD

VTCD

Reset

Output

Note: Logic 1 is in tristate when EN = 0,

VTCD 0.675 * VDD

tD2

Figure 45. Undervoltage Detection with Independent Reset Signal Control

This circuit monitors VDD for undervoltage. If the VDD

input falls below the detector threshold (VDETâ), then the

capacitor on the CD pin will be immediately discharged

resulting in the reset output changing to its active state

indicating that an undervoltage event has been detected. The

addition of a logic gate (Logic 1) provides for reset output

control which is independent of VDD. If the output of the

logic gate is tristated the undervoltage detector will behave

normally. If the tristate is deâasserted, the logic gate will pull

the CD pin low resulting in the Reset Output pin changing to

an active state. This independent control is useful in power

supply sequencing applications when the Reset Output is

tied to the enable input of an LDO or DCâDC converter.

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