SCY99091FCT2G Datasheet, PDF(16/26 Page) ON Semiconductor – Voltage Detector Series with Programmable Delay

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SCY99091FCT2G Datasheet, PDF (16/26 Pages) ON Semiconductor – Voltage Detector Series with Programmable Delay

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NCP302, NCP303

OPERATING DESCRIPTION

The NCP302 and NCP303 series devices consist of a

precision voltage detector that drives a time delay generator.

Figures 37 and 38 show a timing diagram and a typical

application. Initially consider that input voltage Vin is at a

nominal level and it is greater than the voltage detector upper

threshold (VDET+). The voltage at Pin 5 and capacitor CD

will be at the same level as Vin, and the reset output (Pin 1)

will be in the high state for active low devices, or in the low

state for active high devices. If there is a power interruption

and Vin becomes significantly deficient, it will fall below the

lower detector threshold (VDETâ) and the external time

delay capacitor CD will be immediately discharged by an

internal NâChannel MOSFET that connects to Pin 5. This

sequence of events causes the Reset output to be in the low

state for active low devices, or in the high state for active

high devices. After completion of the power interruption,

Vin will again return to its nominal level and become greater

than the VDET+. The voltage detector will turn off the

NâChannel MOSFET and allow pullup resistor RD to charge

external capacitor CD, thus creating a programmable delay

for releasing the reset signal. When the voltage at Pin 5

exceeds the inverter/buffer threshold, typically 0.675 Vin,

the reset output will revert back to its original state. The reset

output time delay versus capacitance is shown in Figures 30

through 32. The voltage detector and inverter/buffer have

builtâin hysteresis to prevent erratic reset operation.

Although these device series are specifically designed for

use as reset controllers in portable microprocessor based

systems, they offer a costâeffective solution in numerous

applications where precise voltage monitoring and time

delay are required. Figures 38 through 46 show various

application examples.

Input Voltage, Pin 2

Vin

VDET+

VDETâ

Capacitor, Pin 5

Vin

0.675 Vin

Reset Output (Active Low), Pin 1

Vin

VDETâ

Reset Output (Active High), Pin 1

Vin

VDETâ

tD2

Figure 37. Timing Waveforms

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