AMIS-49587_P2 Datasheet, PDF (18/55 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS--49587
architecture optimized for IO handling. For most of the
instructions, the machine is able to perform one instruction
per clock cycle. The microcontroller contains the necessary
hardware to implement interrupt mechanisms, timers and is
able to perform byte multiplication over one instruction
cycle. The microcontroller is programmed to handle the
physical layer (chip synchronization), and the MAC layer
conform to IEC 61334--5--1. The program is stored in a
masked ROM. The RAM contains the necessary space to
store the working data. The back--end interface is done
through the Serial Communication Interface block. This
back--end is used for data transmission with the application
micro controller (containing the application layer for
concentrator, power meter, or other functions) and for the
definition of the modem configuration.
5.2.4 Local Port
The controller uses 3 output ports to inform about the
actual status of the PLC communication. RX_DATA
indicates if Receiving is in progress, or if AMIS--49587 is
waiting for synchronization, or of it configures. CRC
indicates if the received frames are valid (CRC = OK).
TX_DATA / PRE_SLOT is the output for either the
transmitting data (TX_DATA) or a synchronization signal
with the time--slots (PRE_SLOT).
5.2.5 Serial Communication Interface
The local communication is a half duplex asynchronous
serial link using a receiving input (RxD) and a transmitting
output (TxD). The input port T_REQ is used to manage the
local communication with the application micro controller
and the baud rate can be selected depending on the status of
two inputs BR0, BR1. These two inputs are taken in account
after an AMIS--49587 reset. Thus when the application
micro controller wants to change the baud rate, it has to set
the two inputs and then provoke a reset.
6 DETAILED HARDWARE DESCRIPTION
6.1 CLOCK AND CONTROL
According to the IEC 61334--5--1 standard, the frame data
is transmitted at the zero crossing of the mains voltage. In
order to recover the information at the zero crossing, a zero
crossing detection of the mains is performed. A
phase--locked loop (PLL) structure is used in order to allow
a more reliable reconstruction of the synchronization. The
output of this block is the clock signal CHIP_CLK, 8 times
over sampled with the bit rate. The oscillator makes use of
a precise 24 MHz quartz. This clock signal together with
CHIP_CLK is fed into the Clock Generator and time block.
Here several internal clock signals and timings are obtained
by the use of a programmed division scheme.
Clock and Control
M50Hz_IN
Zero
crossing
PLL
CHIP_CLK _{Clock Generator}
& Timer
OSC
Figure 11. Clock and Control Block
XIN XOUT
6.1.1 Zero Crossing Detector
M50HZ_IN is the mains frequency analog input pin. The
signal is used to detect the zero crossing of the 50 or 60 Hz
sine wave. This information is used, after filtering with the
internal PLL, to synchronize frames with the mains
frequency. In case of direct connection to the mains it is
advised to use a series resistor of 1 MΩ in combination with
two external clamp diodes in order to limit the current
flowing through the internal protection diodes.
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