AMIS-49587_P2 Datasheet, PDF (17/55 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS--49587
the frame is correct, it is passed to the external
processor.
♦ Test Mode:
The Test Mode is used to test the compliance of a
PLC modem conforms to CENELEC. EN 50065--1
by a Continuous broadcast of f_S or f_M.
5.2 FUNCTIONAL DESCRIPTION
The block diagram below represents the main functional
units of the AMIS--49587:
TO Power Amplifier
TX_ENB
TX_OUT
ALC _ IN
Transmitter (S--FSK Modulator)
LP
Filter
D/A
FROM Line Coupler
RX _OUT
RX _IN
Receiver (S-- FSK Demodulator)
AAF
AGC
A/D
REF_OUT
REF
Transmit Data
& Sine Synthesizer
S--FSK
Demodulator
M50Hz_IN
Clock and Control
Zero
crossing
PLL
Clock Generator
& Timer
OSC
AMIS--49587
Communication Controller
ARM
Risc
Core
Serial
Comm.
Interface
Local Port
Test
5
Control
POR
Watchdog
Timer 1 & 2
TxD
RxD
T_REQ
BR 0
BR 1
TO Application
Micro Controller
RX _DATA
CRC
TX_DATA / PRE _SLOT
JTAG I /F
TEST
RESB
Data
RAM
Program
ROM
Interrupt
Control
VDDA VSSA VDDD VSSD
XIN XOUT
Figure 9. S--FSK Modem AMIS--49587 Block Diagram
PC20091019.2
5.2.1 Transmitter
The AMIS--49587 Transmitter function block prepares
the communication signal which will be sent on the
transmitting channel during the transmitting phase. This
block is connected to a power amplifier which injects the
output signal on the mains through a line--coupler.
5.2.2 Receiver
The analog signal coming from the line--coupler is low
pass filtered in order to avoid aliasing during the
conversion. Then the level of the signal is automatically
adapted by an automatic gain control (AGC) block. This
operation maximizes the dynamic range of the incoming
signal. The signal is then converted to its digital
representation using sigma delta modulation. From then on,
the processing of the data is done in a digital way. By using
dedicated hardware, a direct quadrature demodulation is
performed. The signal demodulated in the base band is then
low pass filtered to reduce the noise and reject the image
spectrum.
Clock and Control
According to the IEC--61334--5--1 standard, the frame
data is transmitted at the zero crossing of the mains voltage.
In order to recover the information at the zero crossing, a
zero crossing detection of the mains is performed. A
phase--locked loop (PLL) structure is used in order to allow
a more reliable reconstruction of the synchronization. This
PLL permits as well a safer implementation of the
”repetition with credit” function (also known as chorus
transmission). The clock generator makes use of a precise
quartz oscillator master. The clock signals are then obtained
by the use of a programmed division scheme. The support
circuits are also contained in this block. The support circuits
include the necessary blocks to supply the references
voltages for the AD and DA converters, the biasing currents
and power supply sense cells to generate the right power off
and startup conditions.
24 bit @ 1200 baud
20 ms
Figure 10. Data Stream is in Sync with Zero
Crossings of the Mains (Example for 50 Hz)
5.2.3 Communication Controller
The Communication Controller block includes the
micro--processor, its peripherals: RAM, ROM, UART,
TIMER, and the Power on reset. The processor uses the
ARM Reduced Instruction Set Computer (RISC)
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