DAC1008D650 Datasheet, PDF (86/98 Pages) NXP Semiconductors – Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1008D650
2×, 4× or 8× interpolating DAC with JESD204A
Table 182. LN2_CFG_8 register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN2_N'[4:0]
R
-
Description
number of bits per sample minus 1
Table 183. LN2_CFG_9 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN2_S[4:0]
R
-
Description
number of samples per converter per frame cycle
minus 1
Table 184. LN2_CFG_10 register (address 0Ah) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
LN2_HD
R
-
4 to 0 LN2_CF[4:0]
R
-
Description
high density
number of control words per frame cycle
Table 185. LN2_CFG_11 register (address 0Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN2_RES1[7:0]
R
-
Description
lane 2 reserved field
Table 186. LN2_CFG_12 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN2_RES2[7:0]
R
-
Description
lane 2 reserved field
Table 187. LN2_CFG_13 register (address 0Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN2_FCHK[7:0]
R
-
Description
lane 2 checksum
Table 188. LN3_CFG_0 register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 0 LN3_DID[7:0]
R
-
Description
lane 3 device ID
Table 189. LN3_CFG_1 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
3 to 0 LN3_BID[3:0]
R
-
Description
lane 3 bank ID
Table 190. LN3_CFG_2 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
4 to 0 LN3_LID[4:0]
R
-
Description
lane 3 lane ID
DAC1008D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2010
© NXP B.V. 2010. All rights reserved.
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