DAC1008D650 Datasheet, PDF (4/98 Pages) NXP Semiconductors – Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
6. Pinning information
6.1 Pinning
DAC1008D650
2×, 4× or 8× interpolating DAC with JESD204A
terminal 1
index area
SDO 1
SDIO 2
SCLK 3
V_DDD(1V8) 4
SCS_N 5
RESET_N 6
n.c. 7
VIRES 8
GAPOUT 9
V_DDA(1V8) 10
V_DDA(1V8) 11
AGND 12
AUXBN 13
AUXBP 14
V_DDA(3V3) 15
AGND 16
DAC1008D650HN
48 n.c.
47 V_DDD(1V8)
46 MDS_N
45 MDS_P
44 V_DDA(1V8)
43 AGND
42 CLKINN
41 CLKINP
40 AGND
39 V_DDA(1V8)
38 V_DDA(1V8)
37 AGND
36 AUXAN
35 AUXAP
34 V_DDA(3V3)
33 AGND
Fig 2. Pin configuration
Transparent top view
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6.2 Pin description
Table 2. Pin description
Symbol
Pin
SDO
1
SDIO
2
SCLK
3
V_DDD(1V8)
4
SCS_N
5
RESET_N
6
n.c.
7
VIRES
8
GAPOUT
9
V_DDA(1V8)
10
V_DDA(1V8)
11
Type^[1]
O
I/O
I
P
I
I
-
I/O
I/O
P
P
Description
SPI data output
SPI data input/output
SPI clock
digital supply voltage 1.8 V
SPI chip select (active LOW)
general reset (active LOW)
not connected
DAC biasing resistor
bandgap input/output voltage
analog supply voltage 1.8 V
analog supply voltage 1.8 V
DAC1008D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2010
© NXP B.V. 2010. All rights reserved.
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