DAC1008D650 Datasheet, PDF (30/98 Pages) NXP Semiconductors – Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1008D650
2×, 4× or 8× interpolating DAC with JESD204A
Table 14. I_O(fs) coarse adjustment
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
Decimal
Binary
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
10
1010
11
1011
12
1100
13
1101
14
1110
15
1111
I_O(fs) (mA)
1.6
3.0
4.4
5.8
7.2
8.6
10.0
11.4
12.8
14.2
15.6
17.0
18.5
20.0
21.0
22.0
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 29
“DAC_A_CFG_2 register (address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0]
(register 0Dh; see Table 32 “DAC_B_CFG_2 register (address 0Dh) bit description”)
define the fine variation of the full-scale current (see Table 15).
Table 15. I_O(fs) fine adjustment
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0]
Decimal
Two’s complement
−32
10 0000
...
...
0
00 0000
...
...
31
01 1111
Delta I_O(fs)
−10 %
...
0
...
+10 %
The coding of the fine gain adjustment is two’s complement.
10.10 Digital offset correction
When the DAC1008D650 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common-mode level at the output of the DAC.
It adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (register 09h; see Table 28
“DAC_A_CFG_1 register (address 09h) bit description” and register 0Bh; see Table 30
“DAC_A_CFG_3 register (address 0Bh) bit description”) and to “DAC_B_OFFSET[11:0]”
DAC1008D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2010
© NXP B.V. 2010. All rights reserved.
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