DAC1008D650 Datasheet, PDF (55/98 Pages) NXP Semiconductors – Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1008D650
2×, 4× or 8× interpolating DAC with JESD204A
Table 76. Lane common-mode voltage adjustment
Register 16h: SET_VCM_VOLTAGE
Decimal
SET_VCM_VOLTAGE
15
1111
14
1110
13
1101
12
1100
11
1011
10
1010
9
1001
8
1000
7
0111
6
0110
5
0101
4
0100
3
0011
2
0010
1
0001
0
0000
V_com (V)
1.40
1.36
1.31
1.26
1.21
1.16
1.12
1.07
1.02
0.97
0.92
0.87
0.82
0.78
0.73
0.68
Table 77. SYNC common-mode voltage adjustment
Register 17h: SET_SYNC
Decimal
SET_SYNC_VCOM[2:0]
7
111
6
110
5
101
4
100
3
011
2
010
1
001
0
000
V_com (V)
1.46
1.36
1.27
1.17
1.07
0.98
0.88
0.79
Table 78. SYNC swing voltage adjustment
Register 17h: SET_SYNC
Decimal
SET_SYNC_LEVEL[2:0]
7
111
6
110
5
101
4
100
3
011
2
010
1
001
0
000
Single-ended output voltage (V)
0.48
0.42
0.36
0.30
0.24
0.18
0.12
0.06
DAC1008D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2010
© NXP B.V. 2010. All rights reserved.
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