DAC1008D650 Datasheet, PDF (40/98 Pages) NXP Semiconductors – Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1008D650
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.2 Page 0 bit definition detailed description
Please refer to Table 18 for a register overview for page 0. In the following tables, all the
values emphasized in bold are the default values.
Table 19. COMMON register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
SPI_3W
R/W
0
1
6
SPI_RST
R/W
0
1
2
DF
R/W
0
1
1
PD_ALL
R/W
0
1
0
GAP_PD
R/W
0
1
Description
serial interface bus type
4 wire SPI
3 wire SPI
serial interface reset
no reset
performs a reset on all registers except 0x00
data format
signed (two’s compliment) format
unsigned format
power-down
no action
all circuits (digital and analog) are switched off
internal bandgap power-down
no action
internal bandgap references are switched off
Table 20. TXCFG register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
NCO_EN
R/W
0
1
6
NCO_LP_SEL
R/W
0
1
5
INV_SINE_EN
4 to 2 MODE[2:0]
R/W
0
1
R/W
000
001
010
011
100
Description
NCO
disabled (the NCO phase is reset to 0)
enabled
low-power NCO
NCO may use all 32 bits
NCO frequency and phase given by the five
MSBs of the registers 06h and 08h respectively
x / (sin x) function
disabled
enabled
modulation
dual DAC: no modulation
positive upper single sideband up-conversion
positive lower single sideband up-conversion
negative upper single sideband up-conversion
negative lower single sideband up-conversion
DAC1008D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2010
© NXP B.V. 2010. All rights reserved.
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