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| PSMN1R6-40YLC Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology | |||
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NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 m⦠logic level MOSFET in LFPAK using
NextPower technology
Symbol
Parameter
Conditions
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 20 V; VGS = 10 V;
Fig. 14; Fig. 15
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 14
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 14
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 20 V; Fig. 14
Ciss
input capacitance
VDS = 20 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
td(off)
turn-off delay time
tf
fall time
Qoss
output charge
VGS = 0 V; VDS = 20 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V; Fig. 18
Qr
recovered charge
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V
ta
reverse recovery rise VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
time
VDS = 20 V; Fig. 18
tb
reverse recovery fall
time
Min Typ Max Unit
-
126 -
nC
-
59
-
nC
-
115 -
nC
-
17.7 -
nC
-
12.5 -
nC
-
5.2 -
nC
-
15.3 -
nC
-
2.4 -
V
-
7790 -
pF
-
1063 -
pF
-
409 -
pF
-
41
-
ns
-
48
-
ns
-
86
-
ns
-
42
-
ns
-
38.7 -
nC
-
0.77 1.1 V
-
44
-
ns
-
62
-
nC
-
26
-
ns
-
18
-
ns
PSMN1R6-40YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
22 August 2012
© NXP B.V. 2012. All rights reserved
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