PIP213-12M Datasheet, PDF (5/21 Pages) NXP Semiconductors – DC-to-DC converter power train

NXP Semiconductors
PIP213-12M
DC-to-DC converter powertrain
8.3 Upper driver operation
The gate drive to the upper MOSFET is provided by a bootstrap capacitor (typically
100 nF) that is placed between the CBP and CBN pins. This capacitor is charged via an
internal boost switch to a voltage within a few millivolts of V_DDC up to a maximum of 12 V
(this is to prevent excessive gate charge losses when V_DDC > 12 V). The upper MOSFET
will be switched according to PWM input once the boost capacitor voltage is above
V_th(CBP-CBN) on. When ever the voltage is below V_th(CBP-CBN) off the upper MOSFET will
remain off.
8.4 V_DDG regulator
The gate drive voltage level to the lower MOSFET is set by the voltage on the V_DDG pin. A
1 µF capacitor must be connected between this pin and V_SSC. For minimum power loss
within the PIP213-12M, an external power supply of between 5 V and 12 V must be
connected to this pin. The optimum value for this voltage is dependent on the application
but in the majority of cases a 5 V supply is recommended; see Figure 11. In cases where
the V_DDG maximum voltage will not be exceeded, the V_DDG pin can be connected to the
V_DDC pin and the V_DDG capacitor can be omitted; see Figure 13.
When V_DDC is connected to a supply greater than 9 V, an internal 6.5 V regulator
connected to V_DDG can be used to provide the gate drive for the lower MOSFET;
see Figure 12. The V_DDG regulator is enabled by leaving the VDDG_EN pin open resulting
in this pin being pulled internally to 5 V. If an external supply is to be connected to V_DDG
then the VDDG_EN pin must be pulled low by connecting to V_SSC to disable the internal
V_DDG regulator.
Table 3. V_DDG biasing
VDDG_EN
V_DDG
Open circuit
internal 6.5 V regulator used (V_DDC > 9 V)
V_SSC
connection to external supply required
8.5 3-state function
If the input to VI from the PWM controller becomes high impedance, then the VI input is
driven to 2.5 V by an internal voltage divider. A voltage on the VI pin that is in-between the
V_IH and V_IL levels and present for longer than t_d(3-state), causes both MOSFETs to be
turned off. Normal operation commences once the VI input is outside this window for
longer than t_d(3-state).
8.6 Automatic Dead-time Reduction (ADR)
Protection against cross-conduction (shoot-through) is achieved via by a delay (or
dead-time) between the switching off of one MOSFET and the switching on of the other
MOSFET. The automatic dead-time reduction feature continuously monitors the body
diode of the lower MOSFET adjusting the dead-time to minimize body diode conduction.
This reduces power loss in both the upper and lower MOSFETs due to the reduction in
body diode conduction and reverse recovery charge. The lower power dissipation leads to
higher system efficiency and enables higher frequency operation.
PIP213-12M_1
Product data sheet
Rev. 01 — 25 September 2007
© NXP B.V. 2007. All rights reserved.
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