PIP213-12M Datasheet, PDF (4/21 Pages) NXP Semiconductors – DC-to-DC converter power train

NXP Semiconductors
PIP213-12M
DC-to-DC converter powertrain
7.2 Pin description
Table 2. Pin description
Symbol
Pin
V_DDC
V_DDO
V_SSC
V_SSO
VI
4
8, 11 to 20, pad 2
1, 7, 51, pad 1
22 to 41
56
VO
42 to 50, pad 3
VO_SENSE 21
Type
-
I
-
-
I
O
O
CBP
5
-
CBN
10
-
VDDG_EN
2
I
V_DDG
3
-
PRDY
53
O
REG5V
54
O
DISABLE
55
I/O
n.c.
6, 9, 52
-
Description
control circuit supply voltage
output stage supply voltage
control circuit ground
output stage ground supply voltage
pulse width modulation input
output voltage
sense connection to VO often required for remote
current sensing
connection to bootstrap capacitor
connection to bootstrap capacitor
enables internal 6.5 V regulator for V_DDG
gate driver supply voltage
indicates that V_DDC is above the UVLO
(UnderVoltage Lockout) level (open drain)
5 V regulated supply output
disable driver function (active LOW)
not connected - leave open or connected to GND
on PCB (Printed-Circuit Board) layout
8. Functional description
8.1 Basic operation
The PIP213-12M combines two MOSFET’s and a MOSFET driver in a thermally
enhanced low inductance package for use in high frequency and high efficiency
synchronous buck DC-to-DC converters; see Figure 2. The two MOSFETs are connected
in a half bridge configuration between V_DDO and V_SSO. The mid point of the two transistors
is V_O which is connected to the output of DC-to-DC converter via an inductor. A logic
HIGH signal on the VI pin causes the lower MOSFET to be switched off and the upper
MOSFET to be switched on. Current will then flow from the supply (V_DDO), through the
upper MOSFET and the inductor (L_o(ext)) to the output.
A logic LOW signal on the VI pin causes the upper MOSFET to be turned off and the lower
MOSFET to be switched on. Current then flows from the power ground (V_SSO), through
the lower MOSFET and the inductor (L_o(ext)), to the output. The output voltage is
determined by the ratio of the times that the upper and lower MOSFETs conduct.
8.2 UnderVoltage Lockout (UVLO)
The UVLO function ensures the correct operation of the control circuit during a power-up
and power-down sequence. Power to the control circuit is provided by the V_DDC pin. This
voltage is internally monitored to ensure that if V_DDC is below the UVLO threshold, the
DISABLE pin is internally pulled LOW and both MOSFETs are off. This is indicated by the
power ready (PRDY) flag, an open drain output that is pulled LOW whenever V_DDC is
below the UVLO threshold.
PIP213-12M_1
Product data sheet
Rev. 01 — 25 September 2007
© NXP B.V. 2007. All rights reserved.
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