74HC259-Q100 Datasheet, PDF (5/20 Pages) NXP Semiconductors – 8-bit addressable latch

NXP Semiconductors
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Table 4.
LE
L
H
L
H
Operating mode select table^[1]
MR
Mode
H
Addressable latch mode
H
Memory mode
L
Demultiplexer mode
L
Reset mode
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
V_CC
supply voltage
I_IK
input clamping current
V_I < 0.5 V or V_I > V_CC + 0.5 V
I_OK
output clamping current
V_O < 0.5 V or V_O > V_CC + 0.5 V
I_O
output current
V_O = 0.5 V to V_CC + 0.5 V
0.5
+7.0
V
[1] _-
20
mA
[1] _-
20
mA
-
25
mA
I_CC
I_GND
T_stg
P_tot
supply current
ground current
storage temperature
total power dissipation
-
70
65
[2] _-
+70
mA
-
mA
+150
C
500
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 package: P_tot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: P_tot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: P_tot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 July 2012
© NXP B.V. 2012. All rights reserved.
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