74HC259-Q100 Datasheet, PDF(10/20 Page) NXP Semiconductors

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74HC259-Q100 Datasheet, PDF (10/20 Pages) NXP Semiconductors – 8-bit addressable latch

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NXP Semiconductors

74HC259-Q100; 74HCT259-Q100

8-bit addressable latch

Table 8. Dynamic characteristics â¦continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.

Symbol Parameter

Conditions

25 ï°C

ï40 ï°C to +85 ï°C ï40 ï°C to +125 ï°C Unit

Min Typ[1] Max Min Max

Min

Max

tsu

set-up time D, An to LE;

see Figure 10 and

Figure 11

VCC = 4.5 V

17 10 -

- ns

hold time

D to LE; see Figure 10

and Figure 11

VCC = 4.5 V

0 ï8 -

- ns

An to LE; see Figure 10

and Figure 11

VCC = 4.5 V

0 ï4 -

- ns

CPD

power

fi = 1 MHz;

[4] -

- pF

dissipation

VI = GND to VCC ï 1.5 V

capacitance

[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).

[2] tpd is the same as tPLH and tPHL.

[3] tt is the same as tTHL and tTLH.

[4] CPD is used to determine the dynamic power dissipation (PD in ïW).

PD = CPD ï´ VCC2 ï´ fi ï´ N + ï(CL ï´ VCC2 ï´ fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

ï(CL ï´ VCC2 ï´ fo) = sum of the outputs.

11. Waveforms

VCC

D input

GND

VOH

Qn output

VOL

tPHL

tPLH

001aah123

Fig 6.

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Data input to output propagation delays

74HC_HCT259_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 â 30 July 2012

10 of 20

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