74HC259-Q100 Datasheet, PDF (3/20 Pages) NXP Semiconductors – 8-bit addressable latch

NXP Semiconductors
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
1 A0
2 A1
3 A2
1-of-8
DECODER
14 LE
15 MR
13 D
Fig 3. Functional diagram
5. Pinning information
Q0 4
Q1 5
Q2 6
Q3 7
8 LATCHES _{Q4 9}
Q5 10
Q6 11
Q7 12
mna571
5.1 Pinning
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
74HC259-Q100
74HCT259-Q100
16 V_CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
9 Q4
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Fig 4. Pin configuration (SO16 and TSSOP16)
terminal 1
index area
74HC259-Q100
74HCT259-Q100
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND⁽¹⁾
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
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Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 5. Pin configuration (DHVQFN16)
74HC_HCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 July 2012
© NXP B.V. 2012. All rights reserved.
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