74HC259-Q100 Datasheet, PDF (11/20 Pages) NXP Semiconductors – 8-bit addressable latch

NXP Semiconductors
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
V_CC
An input
GND
V_OH
Qn output
V_OL
V_M
t_PHL
V_M
t_PLH
001aah122
Fig 7.
Measurement points are given in Table 9.
V_OL and V_OH are typical voltage output levels that occur with the output load.
Address input to output propagation delays
V_CC
D input
GND
V_CC
LE input
GND
V_OH
Qn output
V_OL
V_M
t_W
t_PHL
V_Y
V_M
V_X
t_THL
t_PLH
Fig 8.
Measurement points are given in Table 9.
V_OL and V_OH are typical voltage output levels that occur with the output load.
Enable input to output propagation delays and pulse width
t_TLH
001aaj446
V_CC
MR input
GND
V_OH
Qn output
V_OL
V_M
t_W
t_PHL
V_M
001aah124
Fig 9.
Measurement points are given in Table 9.
V_OL and V_OH are typical voltage output levels that occur with the output load.
Master reset input to output propagation delays
74HC_HCT259_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 July 2012
© NXP B.V. 2012. All rights reserved.
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