PSMN025-100D Datasheet, PDF (3/11 Pages) NXP Semiconductors – N-channel TrenchMOS SiliconMAX standard level FET

NXP Semiconductors
PSMN025-100D
N-channel TrenchMOS SiliconMAX standard level FET
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Avalanche ruggedness
E_DS(AL)S
non-repetitive
V_GS = 10 V; T_j(init) = 25 °C; I_D = 40 A; V_sup ≤ 25 V;
drain-source avalanche unclamped; t_p = 100 µs; R_GS = 50 Ω
energy
I_AS
non-repetitive
V_sup ≤ 25 V; V_GS = 10 V; T_j(init) = 25 °C; R_GS = 50 Ω;
avalanche current
unclamped; see Figure 4
Min Max Unit
-
260 mJ
-
47
A
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100 125
Mounting Base temperature, Tmb (C)
lma016
150 175
1000 ^{Peak Pulsed Drain Current, IDM (A)}
RDS(on) = VDS/ ID
100
10
D.C.
1
lma017
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.1
1
10
100
Drain-Source Voltage, VDS (V)
1000
Fig 1. Continuous drain current as a function of
mounting base temperature
Normalised Power Derating, PD (%)
100
lma015
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100 125 150 175
Mounting Base temperature, Tmb (C)
Fig 2. Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
Maximum Avalanche Current, IAS (A)
100
lma029
10
Tj prior to avalanche = 150 C
25 C
1
0.001
0.01
0.1
1
10
Avalanche time, tAV (ms)
Fig 3. Normalized total power dissipation as a
function of mounting base temperature
Fig 4. Maximum permissible non-repetitive avalanche
current as a function of avalanche time
PSMN025-100D_3
Product data sheet
Rev. 03 — 20 November 2008
© NXP B.V. 2008. All rights reserved.
3 of 11