GTL2010 Datasheet, PDF (3/20 Pages) NXP Semiconductors – 10-bit GTL Processor Voltage Clamp

NXP Semiconductors
6. Pinning information
6.1 Pinning
GTL2010
10-bit bidirectional low voltage translator
GND 1
SREF 2
S1 3
S2 4
S3 5
S4 6
S5 7
S6 8
S7 9
S8 10
S9 11
S10 12
GTL2010PW
24 GREF
23 DREF
22 D1
21 D2
20 D3
19 D4
18 D5
17 D6
16 D7
15 D8
14 D9
13 D10
002aac057
Fig 2. Pin configuration for TSSOP24
terminal 1
index area
S2 1
S3 2
S4 3
S5 4
S6 5
S7 6
GTL2010BS
18 D2
17 D3
16 D4
15 D5
14 D6
13 D7
Transparent top view
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Fig 3. Pin configuration for HVQFN24
6.2 Pin description
Table 3. Pin description
Symbol
Pin
Description
TSSOP24
HVQFN24
GND
1
22^[1]
ground (0 V)
SREF
2
23
source of reference transistor
S1 to S10
3, 4, 5, 6, 7, 8, 9, 24, 1, 2, 3, 4, 5, 6, Port S1 to Port S10
10, 11, 12
7, 8, 9
D1 to D10
22, 21, 20, 19, 18, 19, 18, 17, 16, 15, Port D1 to Port D10
17, 16, 15, 14, 13 14, 13, 12, 11, 10
DREF
23
20
drain of reference transistor
GREF
24
21
gate of reference transistor
[1] HVQFN24 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
GTL2010_6
Product data sheet
Rev. 06 — 3 March 2008
© NXP B.V. 2008. All rights reserved.
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